Parallel Processing Unit for Sequential Calculation Execution
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Solution Overview
Problem
Existing parallel processing devices are not suitable for performing very long sequential calculations in parallel, as they are primarily designed for operations like filtering and Fast Fourier Transform, and lack the capabilities of central processing units (CPUs).
Innovation Solution
A parallel processing unit comprising multiple main processing units and a decision processing unit, where each main processing unit performs calculations, adds outputs, and compares results, while the decision processing unit aggregates outputs, delays signals, and makes comparisons to facilitate parallel execution of sequential calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional parallel processing devices are used for sequential calculations, then filtering and FFT operations can be performed efficiently, but the device cannot perform very long sequential calculations in parallel
Solution Approach 1:
The processing device is divided into multiple main processing units (MPUs), each capable of independent calculation operations. Each MPU processes a portion of the sequential calculation simultaneously, enabling parallel execution of what would traditionally be sequential operations
Solution Approach 2:
The main processing units are designed with universal functionality to perform various CPU operations including arithmetic calculations, comparisons, and control flow decisions. This multi-functionality allows the same hardware structure to handle diverse sequential calculation tasks that were previously CPU-exclusive
2Speed
If multiple main processing units are used to perform calculations in parallel, then calculation speed improves, but the complexity of aggregating and managing outputs increases
Solution Approach 1:
Multiple adder units are employed to aggregate outputs from different main processing units. These adders combine intermediate results in a systematic manner, merging the parallel computation streams into a unified output that represents the complete sequential calculation result
Solution Approach 2:
Delay units are introduced as intermediary components between the parallel processing stages and the final aggregation point. These delay units synchronize the timing of signals from different MPUs, ensuring that outputs are ready for aggregation at the appropriate clock cycles and managing the complexity of parallel output coordination
3Device complexity
If sequential calculations are performed on traditional parallel processing devices, then the device structure remains simple, but the number of cycles required to complete tasks increases significantly
Solution Approach 1:
The processing device employs dynamic control mechanisms including comparators and delay units that adapt the flow of data through the pipeline based on calculation progress. This dynamic structure allows the system to maintain simple hardware while efficiently managing the timing and coordination required for parallel sequential calculations, reducing the number of cycles needed
Data Source
AI summary
A parallel processing unit includes a plurality of main processing units and a decision processing unit. Each of the plurality of main processing units includes a main processing calculator for performing a calculation on one or more inputs, a main processing adder for adding an output of the main processing calculator and an output of a decision processing delayer, and a main processing comparator for making a comparison with an output of the main processing adder. The decision processing unit includes a decision processing calculator for adding outputs of the plurality of main processing calculators, a decision processing adder for adding an output of the decision processing calculator and the output of the decision processing delayer, the decision processing delayer for delaying an output of the decision processing adder, and a decision processing comparator for making a comparison with the output of the decision processing adder.