Parallel Redundancy Refresh Circuit for Semiconductor Storage
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Solution Overview
Problem
Semiconductor storage devices face challenges in performing refresh tests on redundancy areas, as they are not configured to allow CBR refresh commands, leading to differences in detected defective bits and increased test time due to sequential refresh operations, which complicates the detection and replacement of unstable memory cells.
Innovation Solution
Implementing a semiconductor storage device with a normal area and a redundancy area refresh circuit that performs CBR refresh operations in parallel, allowing CBR refresh commands for the redundancy area under the same conditions as the normal area, thereby reducing test time and simplifying control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CBR refresh commands are not allowed for redundancy area, then the device structure remains simple, but refresh test cannot be performed under actual usage conditions and test time increases
Solution Approach 1:
The memory cell array is divided into a normal area and a redundancy area, with separate refresh circuits allocated to each area. The refresh control unit selectively activates either the normal area refresh circuit or the redundancy area refresh circuit based on the refresh target, enabling independent refresh operations for each area while maintaining overall system simplicity.
Solution Approach 2:
The refresh control unit is designed to universally handle refresh commands for both normal area and redundancy area by interpreting the same CBR refresh command format. This multi-functional capability allows the device to perform refresh operations under actual usage conditions without requiring separate command sequences, thereby improving detection accuracy while avoiding excessive complexity.
2Productivity
If sequential refresh operations are used for redundancy area, then device complexity remains low, but test time increases significantly
Solution Approach 1:
The normal area refresh circuit and redundancy area refresh circuit are merged into a unified refresh system controlled by a single refresh control unit. This integration enables parallel execution of refresh operations for both areas simultaneously, dramatically improving refresh test speed while avoiding the need for complex separate control mechanisms.
Solution Approach 2:
The refresh system dynamically switches between different operational modes: normal mode for standard refresh operations and test mode for redundancy area verification. This dynamic adaptability allows the system to optimize performance for different scenarios without requiring permanently complex control logic, thereby improving productivity while maintaining manageable device complexity.
3Measurement precision
If different refresh methods are used for normal area and redundancy area, then device structure remains simple, but detection of defective bits becomes inconsistent
Solution Approach 1:
While maintaining the same CBR refresh method for both areas to ensure detection consistency, the patent applies local quality by providing dedicated refresh circuits for each area. This allows each area to be refreshed with identical methodology (ensuring consistent defective bit detection) while maintaining independent circuit paths (simplifying timing control complexity).
Data Source
AI summary
A semiconductor storage device is provided with: a memory cell array which includes a normal area and a redundancy area which replaces a defective memory cell in the normal area; a normal area refresh circuit which performs a CBR refresh operation of a memory cell which is connected to a word line in the normal area; and a redundancy area refresh circuit which performs a CBR refresh operation of a memory cell which is connected to a word line in the redundancy area in parallel with the CBR refresh operation of the memory cell in the normal area.