Parallel Resistive Memory Cell for Low Resistance and Variability
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Solution Overview
Problem
Volatile memory elements in integrated circuits are prone to soft error upsets due to cosmic rays and radioactive impurities, leading to data loss, and traditional non-volatile resistive memory elements require high current for operation and exhibit large variation across memory cells.
Innovation Solution
The implementation of memory cells with resistive memory elements formed in integrated circuits, where multiple resistive memory elements are connected in parallel, reducing the on-state resistance and variability, and using a specific structure with metal layers and oxide layers to achieve lower and more consistent resistive states for data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If traditional non-volatile resistive memory elements are used, then data retention without power is achieved, but high current is required for operation and large variation across memory cells occurs
Solution Approach 1:
The patent divides a single resistive memory element into multiple parallel resistive memory elements (e.g., four elements in parallel). This segmentation reduces the on-state resistance of the overall memory cell while maintaining non-volatile data retention, thereby lowering the current requirement for operation without sacrificing data retention capability.
2Duration of action of stationary object
If traditional non-volatile resistive memory elements are used, then data retention without power is achieved, but large variation across memory cells occurs
Solution Approach 1:
By implementing multiple parallel resistive memory elements, the patent reduces the impact of individual element variations on the overall cell performance. The parallel configuration averages out the resistance variations, leading to more consistent on-state resistance across different memory cells while preserving non-volatile data retention.
3Speed
If volatile memory elements are used, then fast operation is achieved, but soft error upsets occur and data is lost on power loss
Solution Approach 1:
The patent uses multiple parallel resistive memory elements to achieve a configuration that combines advantages of both volatile and non-volatile memory. The parallel structure reduces on-state resistance for faster operation while the non-volatile nature of resistive memory elements ensures data retention without power and resistance to soft error upsets.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the resistance of integrated circuit memory arrays to soft error upsets and reduces the operational current requirements, resulting in a more reliable and stable data storage system with lower on-state resistance variability.
Implementation Method 1
resistive switching memory units made of chalcogenide or metal oxide
Data Source
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Figure 3A
AI summary
A memory cell (208) is disclosed that includes at least two non-volatile resistive memory elements (302) coupled in parallel, preferably via first and second metal layers (304, 306), one of which may be connected to a source-drain region (312) of an access transistor (214). The non-volatile resistive memory elements are capable of existing in different resistive states such that each of the different resistive state represents a different data state. The parallel connection leads to a mean on-state resistance which is lower and less variable.