Parallel Sample Hold Circuits for LADAR Power Reduction
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Solution Overview
Problem
Current LADAR systems face challenges with high power dissipation, large size, high cost, and complexity due to the need for multiple ADCs and DMUX functions for each pixel in detector arrays, leading to thermal and packaging issues, especially for larger arrays.
Innovation Solution
A LADAR system utilizing a bank of parallel sample/hold circuits driven by a low noise amplifier, with sampling points spaced one nanosecond apart, allowing for reduced clock rates and power consumption, enabling a single chip solution using standard CMOS technology and conventional packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple ADCs and DMUX functions are used for each pixel in detector arrays, then sampling resolution and range determination accuracy are improved, but power dissipation increases significantly
Solution Approach 1:
The patent divides the detector array into multiple groups, with each group sharing a common ADC and DMUX. This segmentation reduces the total number of ADCs and DMUX circuits needed, directly lowering power dissipation while maintaining sampling resolution through the shared high-speed conversion resources.
Solution Approach 2:
The patent implements universal ADC and DMUX circuits that serve multiple detector pixels simultaneously. These multi-functional circuits perform the same sampling and conversion functions for different pixel groups, eliminating the need for dedicated ADCs per pixel and significantly reducing overall power consumption.
2Measurement precision
If multiple ADCs and DMUX functions are used for each pixel in detector arrays, then sampling resolution and range determination accuracy are improved, but device size and complexity increase
Solution Approach 1:
The patent segments the detector array into multiple groups that share common ADC and DMUX circuits. This segmentation approach reduces the total number of individual components needed, simplifying the overall device architecture and reducing complexity while maintaining high sampling resolution through shared high-speed conversion paths.
Solution Approach 2:
The patent merges the ADC and DMUX functions into shared circuits that serve multiple detector pixels. By combining these functions at the group level rather than implementing them individually for each pixel, the device complexity is reduced while preserving the necessary sampling resolution and range determination accuracy.
3Measurement precision
If multiple ADCs and DMUX functions are used for each pixel in detector arrays, then sampling resolution and range determination accuracy are improved, but packaging becomes difficult due to thermal and size constraints
Solution Approach 1:
The patent segments the detector array into multiple groups that share common ADC and DMUX circuits. This segmentation reduces the total number of high-power components that need to be packaged, making thermal management easier and simplifying the packaging process while maintaining the sampling resolution benefits of high-speed ADC conversion.
Solution Approach 2:
The patent discards the approach of using individual ADCs per pixel, which creates packaging difficulties. Instead, it recovers the sampling resolution performance by using shared ADCs with sufficient bandwidth, thereby eliminating packaging constraints while maintaining measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power dissipation by 50 to 100 times, eliminates the need for advanced bipolar technology, and simplifies packaging, while achieving sub-nanosecond sampling resolution and accurate range determination with lower costs and thermal considerations.
Implementation Method 1
an optical signal detector converts the optical signal to an electrical signal
Data Source
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AI summary
Disclosed is a LADAR system and a method for operating same. The LADAR system includes circuitry for generating the electrical signal with an optical signal detector using N discrete samples; a bank of M parallel sample/hold circuit unit cells individual ones of which operate with an associated sample/hold clock, where each sample/hold clock is shifted in time by a fixed or programmable amount ?t relative to a sample/hold clock of an adjacent sample/hold circuit unit cell; and further includes circuitry for sequentially coupling a sampled value of the electrical signal from a first output of individual ones of at least some of the M parallel sample/hold circuit unit cells to an analog to digital converter circuit. Each of the M parallel sample/hold circuit unit cells has a second output for outputting a digital signal for indicating the state (low or high) during a time that the associated sample/hold clock allowing for time of arrival determination. The LADAR system further includes or is coupled to a signal processor for deriving an image of the object and a range to the object based on signals at the first and second outputs. Assuming an effective sample/hold circuit sampling rate of X samples per second, a sampling rate of each of the M parallel sample/hold circuit unit cells can be X/M samples per second.