Parallel Source Line MRAM Cell Layout for 6 F2 Density
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Solution Overview
Problem
In spin injection magnetization reversal type magnetic random access memory (MRAM), the operating speed is decreased due to the need for all unselected bit lines to be charged to a predetermined potential during a write cycle, especially when the common source line and bit line are perpendicular to each other, limiting the cell size to 8 F^2.
Innovation Solution
The configuration of bit lines and source lines is modified such that the source line runs parallel to the bit lines, allowing the source/drain diffusion layer to connect cells in series, reducing the cell size to approximately 6 F^2 by eliminating the need for source lines between bit lines and enabling the same interconnection layer for both, thereby decreasing the spacing between bit lines and word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the common source line and bit line are arranged perpendicular to each other, then the cell size can be reduced, but all unselected bit lines must be charged to a predetermined potential during write cycle, decreasing the operating speed
Solution Approach 1:
The patent inverts the conventional perpendicular arrangement of source line and bit line to a parallel arrangement. By making the source line run parallel to the bit lines instead of perpendicular, the patent eliminates the need to charge all unselected bit lines during write operations, thereby improving operating speed while maintaining compact cell dimensions through optimized interconnection geometry
2Area of moving object
If the common source line runs between bit lines, then the cell size cannot be made smaller than 8 F^2 due to contact placement constraints
Solution Approach 1:
Instead of placing the source line between bit lines as in conventional designs, the patent positions the source line parallel to and adjacent to the bit lines. This inversion of the interconnection layout allows contacts to be placed more efficiently and reduces the minimum cell size to approximately 6 F^2 by eliminating the need for source lines to run between bit lines
3Ease of manufacture
If additional metal interconnection layers are used to connect source lines and bit lines, then the cell size increases and parasitic resistance increases
Solution Approach 1:
The patent merges the source line and bit line into the same metal interconnection layer, eliminating the need for separate interconnection layers for source and bit lines. This consolidation reduces the total number of metal layers required, decreases parasitic resistance, and reduces cell size to approximately 6 F^2 by removing the vertical stacking requirement for multiple interconnection layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces cell size, decreases parasitic resistance, and allows for faster operating speeds by eliminating the need for additional metal interconnection layers, while maintaining efficient data storage through the magnetoresistive effect.
Implementation Method 1
a first magnetoresistive effect element connected to the first bit line, a second magnetoresistive effect element connected to the second bit line
Data Source
AI summary
A magnetic random access memory includes a first bit line and a second bit line, a source line formed for a group having the first bit line and the second bit line, adjacent to the first bit line, and running in a first direction in which the first bit line and the second bit line run, a first magnetoresistive effect element connected to the first bit line, a second magnetoresistive effect element connected to the second bit line, a first transistor connected in series with the first magnetoresistive effect element, and a second transistor connected in series with the second magnetoresistive effect element. A first cell having the first magnetoresistive effect element and the first transistor and a second cell having the second magnetoresistive effect element and the second transistor are connected together to the source line.