Parallel Power Transistor Gate Control for Uniform Switching Losses
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Solution Overview
Problem
In parallel connections of power transistors, asymmetrical heating occurs due to differences in component properties, leading to uneven switching losses and reduced efficiency, with existing solutions either requiring rapid switching or expensive selection of transistors with similar properties.
Innovation Solution
A method where the gates of power transistors are controlled with different values to ensure one transistor reaches threshold voltage first during switching on and last during switching off, distributing switching losses uniformly across transistors, using an ASIC to manage these control values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power transistors are used in parallel to distribute current, then current capacity is increased, but asymmetrical heating occurs due to component variations causing uneven switching losses
Solution Approach 1:
The patent applies asymmetry by intentionally introducing different control values for each power transistor gate. Instead of treating all transistors equally, the method assigns specific control values (first, second, third control values) that are different from each other and from zero, creating an asymmetric control scheme that compensates for the inherent asymmetry in component variations. This deliberate asymmetry in control signals symmetrizes the switching losses across all transistors.
Solution Approach 2:
The patent changes the control parameter (gate voltage/control value) for each transistor individually. By specifying different control values for each transistor's gate and dynamically adjusting them during switching operations, the method modifies the operating parameters to achieve uniform switching losses. The control values are changed based on the switching state and component characteristics, allowing precise control over each transistor's behavior.
2Loss of energy
If fast switching is implemented to symmetrize switching losses, then switching losses are equalized, but parasitic inductive properties cause additional complications
Solution Approach 1:
The patent applies preliminary action by pre-specifying different control values for each transistor before switching operations begin. The control device is configured in advance with the knowledge that each transistor requires a different control value to achieve symmetrical switching losses. This preliminary configuration allows the system to compensate for component variations before they manifest as unequal heating, rather than reacting to the problem after it occurs.
Solution Approach 2:
The method implements a feedback mechanism where the control values are adjusted based on the switching state and component characteristics. The control device uses information about each transistor's behavior (such as switching losses and temperature) to dynamically adjust the control values, creating a closed-loop system that continuously optimizes the distribution of switching losses across all transistors.
3Loss of energy
If power transistors are selected for high uniformity in properties, then switching losses are evenly distributed, but manufacturing cost increases due to selection effort
Solution Approach 1:
The patent applies self-service by allowing the control device to automatically compensate for component variations without requiring manual selection or matching of transistors. The system uses the inherent variations in component properties as input to its control algorithm, which then automatically adjusts the control values to achieve uniform switching losses. This eliminates the need for expensive pre-selection processes while maintaining even loss distribution.
Solution Approach 2:
Instead of selecting transistors with uniform properties during manufacturing, the patent changes the control parameters (gate voltages) to achieve uniform performance. This parameter adjustment approach allows the use of standard, less expensive transistors with normal manufacturing tolerances, while the control system compensates for variations through dynamic parameter adjustment.
4Device complexity
If a single control value is used for all power transistor gates, then control is simplified, but one transistor carries almost all switching losses due to lowest threshold voltage
Solution Approach 1:
The patent applies segmentation by dividing the control signal into separate, individual control values for each transistor gate. Instead of using a single unified control signal, the method segments the control into multiple independent signals (first control value, second control value, third control value), each tailored to the specific characteristics of its associated transistor. This segmentation allows precise control over each transistor's switching behavior.
Solution Approach 2:
The patent implements local quality by assigning different control characteristics to different transistors based on their individual properties. Each transistor receives a customized control value that is optimized for its specific threshold voltage and switching characteristics. This localized control approach ensures that each transistor operates in an optimal manner, preventing any single transistor from dominating the switching losses.
Data Source
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AI summary
The invention relates to a method for switching a cycle in a power transistor circuit (HB1, HB2, HB3) which has at least two power transistors (M1, M2, M3, M4, M5, M6) connected in parallel, wherein the power transistors (M1, M2, M3, M4, M5, M6) each have gates which, in the method, are controlled with at least three control values (Ig1, Ig2, Ig3, Vg1', Vg2', Vg3') that are different from each other and from zero, wherein, in a switch-on sequence of the parallel-connected power transistors (M1, M2, M3, M4, M5, M6), a first of the power transistors (M1, M2, M3, M4, M5, M6) is initially controlled with a higher control value (Ig1, Ig2, Ig3, Vg1', Vg2', Vg3') than the other power transistor (M1, M2, M3, M4, M5, M6) or the other power transistors (M1, M2, M3, M4, M5, M6), so that a gate voltage (Vg) of the first power transistor (M1, M2, M3, M4, M5, M6) is the first to exceed a threshold voltage (V_TH).