Parallel Transistor Pair for MRAM Read Signal Preservation
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Solution Overview
Problem
Current magnetoresistive random access memory (MRAM) systems face challenges in accurately reading and writing data due to capacitance issues and premature state changes during read operations, leading to increased bit error rates and inefficient data storage.
Innovation Solution
The implementation of a transistor pair comprising a pMOSFET and an nMOSFET connected in parallel to each bit line and word line, allowing for optimized selection and read operations by controlling the conductive state of each transistor to minimize capacitance and ensure accurate voltage sensing across MRAM memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single transistor is used per bit line/word line, then device complexity is reduced, but capacitance is higher causing premature state changes and increased bit error rates
Solution Approach 1:
The patent divides the single transistor function into two separate transistors (first transistor and second transistor) per bit line and word line. This segmentation allows each transistor to handle different voltage levels independently, reducing the total capacitance loaded on the memory cell and preventing premature state changes during read operations, thereby reducing bit error rates.
Solution Approach 2:
The patent introduces a second voltage dimension by using two transistors to provide different voltage levels (first voltage and second voltage) to the bit line and word line. This dimensional approach allows for optimized voltage control during read operations, enabling accurate sensing while minimizing capacitance effects that cause premature state changes.
2Measurement precision
If voltage is applied during read operation, then data can be sensed, but premature state changes occur leading to inaccurate reading
Solution Approach 1:
The patent changes the voltage parameters applied during read operations by using two different voltage levels (first voltage and second voltage) through the respective transistors. This parameter differentiation allows the system to apply sufficient voltage for accurate sensing while controlling the total voltage stress on the memory cell, preventing premature state changes and maintaining data integrity.
Solution Approach 2:
The patent introduces transistors as intermediary elements between the voltage source and the memory cell. These transistors act as controlled switches that regulate voltage application, enabling accurate voltage sensing while preventing excessive voltage that would cause premature state changes, thus protecting data integrity.
3Device complexity
If capacitance is minimized by reducing transistors, then device complexity decreases, but voltage sensing accuracy deteriorates
Solution Approach 1:
The patent applies different qualities to different parts of the circuit by using two transistors with different characteristics (first transistor for bit line, second transistor for word line). Each transistor is optimized for its specific function, allowing accurate voltage sensing while managing capacitance. The local optimization of each transistor's role achieves both reduced capacitance and maintained sensing accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces bit error rates and enhances data storage efficiency by minimizing capacitance and maintaining accurate voltage sensing, allowing for reliable bidirectional writing and reading in MRAM systems.
Implementation Method 1
due to capacitance issues and premature state changes during read operations
Implementation Method 2
magnetoresistive random access memory (MRAM), which uses magnetization to represent stored data
Data Source
AI summary
Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be turned on while the pMOSFET remains on. The nMOSFET adds a resistance which offsets a decreased resistance of the pMOSFET to allow accurate sensing of the voltage across the memory cell.