Parallel Trellis Decoding With Overlapping Subsequence Processing

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Solution Overview

Problem

Current systems face challenges in maximizing the rate of trellis-based methods like Viterbi decoding and turbo equalization, which are computationally intensive, and require mechanisms to enhance flexibility in receiver functionality for signal processing operations.

Innovation Solution

A method and system utilizing a software-defined radio architecture with multiple processors operating in parallel on overlapping subsequences of symbol data sequences, employing trellis structures to generate soft estimates for information bits, and iterating between demodulation and decoding processes to improve processing efficiency and flexibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If trellis-based methods (Viterbi decoding, turbo equalization) are implemented in software-defined radio, then flexibility in receiver functionality is improved, but processing speed and computational efficiency deteriorate due to the computationally intensive nature of these methods

Engineering Contradiction:
Improveflexibility in receiver functionalityVSAvoidprocessing speed
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The received symbol data sequence is divided into multiple overlapping subsequences, with each subsequence processed by a separate processor in parallel. This segmentation enables the computationally intensive trellis-based methods to be distributed across multiple processing units, maintaining software-defined radio flexibility while significantly improving processing speed through parallel execution.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a temporal dimension to the processing architecture by using overlapping subsequences that extend across time. Multiple processors operate simultaneously on different temporal segments of the same data sequence, transforming a single-processor sequential operation into a multi-processor parallel operation, thereby resolving the speed-flexibility contradiction.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple processors operate in parallel on overlapping subsequences, then processing rate is improved, but computational complexity and resource requirements worsen

Engineering Contradiction:
Improveprocessing rateVSAvoidcomputational complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Multiple processors operate on overlapping subsequences rather than disjoint segments. The overlap allows processors to share common computational work and data, reducing redundant calculations. This merging approach enables parallel processing to achieve higher processing rates without proportionally increasing computational complexity, as adjacent processors can reuse computations from overlapping regions.

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If iterative message passing between demodulation and decoding is implemented, then accuracy of soft estimates is improved, but processing time increases

Engineering Contradiction:
Improveaccuracy of soft estimatesVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The iterative message passing process is segmented and distributed across multiple processors operating in parallel. Each processor performs a portion of the iterative computations on its assigned subsequence simultaneously with other processors, maintaining the accuracy benefits of iterative message passing while reducing overall processing time through parallel execution of iterative steps.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8644431B2Parallel execution of trellis-based methods
Publication Date: 2014.02.04 HYPERX HOLDINGS LLC
  • US8644431B2 patent drawing
  • US8644431B2 patent drawing
  • US8644431B2 patent drawing

AI summary

A receiver system and method for recovering information from a symbol data sequence Y. The symbol data sequence Y corresponds to a symbol data sequence X that is transmitted onto the channel by a transmitter. The symbol data sequence X is generated by the transmitter based on associated information bits. At the receiver, a set of two or more processors operate in parallel on two or more overlapping subsequences of the symbol data sequence Y, where each of the two or more overlapping subsequences of the symbol data sequence Y corresponds to a respective portion of a trellis. The trellis describes redundancy in the symbol data sequence Y. The action of operating in parallel generates soft estimates for the associated information bits. The soft estimates are useable to form a receive message corresponding to the associated information bits.