Parallel Upsampling Circuit for High Data Rate Modulation
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Solution Overview
Problem
Existing wideband programmable digital modems are limited by clock speeds of field programmable gated arrays (FPGAs), resulting in low data rates due to prior art systems that can only upsample by a factor of one-third the system clock rate, which is insufficient for high-data-rate applications.
Innovation Solution
A circuit architecture that upsamples a digital data stream by a factor greater than one, using a system clock, a polyphase Nyquist filter, and a numerically controlled oscillator to produce multiple samples per symbol, enabling data rates up to M times the system clock rate, and incorporating a phase rotator sub-circuit and accumulator block for continuous phase modulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If prior art systems use traditional upsampling methods limited to one-third the system clock rate, then the system can operate within FPGA clock speed constraints, but the data rate is insufficient for high-data-rate applications
Solution Approach 1:
The patent divides the upsampling process into multiple parallel stages, where each stage processes a portion of the data stream simultaneously. This segmentation allows the system to achieve higher overall upsampling factors by combining the output of multiple parallel processing paths, thereby increasing data rate without exceeding individual FPGA clock speed constraints.
Solution Approach 2:
The patent transitions from sequential single-path upsampling to parallel multi-dimensional processing by introducing multiple independent processing channels that operate simultaneously. This dimensional expansion in the processing architecture enables the system to multiply the effective data throughput beyond the limitations of a single clock domain.
2Productivity
If the system increases upsampling factor to achieve higher data rates, then productivity improves, but intersymbol interference is introduced that must be removed at the receiver
Solution Approach 1:
The patent applies preliminary filtering and pulse shaping operations before the upsampling process to pre-condition the signal in a way that minimizes the generation of intersymbol interference. By performing this preparatory action upstream in the processing chain, the system achieves high data rates while keeping ISI levels manageable and removable at the receiver.
Data Source
AI summary
A circuit 30 for upsampling and upconverting a high rate signal that is divided into M in phase (I) symbols and M quadrature (Q) symbols. A Nyquist filter 32 upsamples by a factor of k each of the 2M symbols in parallel during one system clock period (CP). The filter 32 has a plurality of 2kM filter components 40, 42, that each provides a continuous output. A plurality of multipliers 50, 52 each upconverts a filter component output with a carrier wave signal 46, 48 that is output from a numerically controlled oscillator 44. A plurality of adders 54 each adds the output of two multipliers 50 to recombine corresponding I and Q samples to output kM samples during a CP. For continuous phase modulation, N parallel bits are input into the filter 32, upsampled in one CP, and accumulated and modulated 82 in parallel in one CP. For analog processing, M (I) and M (Q) symbols are input into an FIR filter 77a, 77b for upsampling, and decimated at a MUX/DAC block 78 for subsequent analog upconversion.