Parallel Viterbi Decoder Using Shared Memory for High-Speed Decoding
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Solution Overview
Problem
Current Viterbi decoders face challenges in achieving high-speed decoding without increasing manufacturing costs or power consumption, as duplicating decoders or overclocking leads to hardware cost increases and high power consumption.
Innovation Solution
A continuous parallel Viterbi decoder with input means for computing Trellis paths, output means for backtracking, shared memory for storing paths, and coordination means for simultaneous read/write operations, allowing for high-speed decoding without doubling hardware or increasing clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two parallel Viterbi decoders are used to achieve high-speed decoding, then decoding speed is improved, but hardware occupation area and manufacturing cost increase
Solution Approach 1:
The patent merges two Viterbi decoding operations into a single decoder by implementing parallel processing of two coded blocks within one decoder unit. The coordination means enables two independent decoding processes to share the same hardware resources (memory, arithmetic units) by time-multiplexing and coordinate management, thus achieving high-speed decoding without duplicating the entire decoder hardware.
Solution Approach 2:
The patent introduces a new dimension of parallelism by processing two coded blocks simultaneously within a single decoder through coordinate means that manage multiple code block identifiers and path computations. This transforms the traditional single-block sequential processing into a multi-block parallel processing framework without requiring multiple physical decoders.
2Productivity
If clock frequency is increased to achieve high-speed decoding, then decoding speed is improved, but power consumption increases
Solution Approach 1:
The patent segments the decoding process into independent stages that can be coordinated and managed efficiently. By dividing the continuous bitstream into multiple coded blocks with independent processing paths, the system can process multiple blocks in parallel within a single decoder clock cycle, achieving higher throughput without increasing clock frequency.
Solution Approach 2:
The patent changes the processing parameter from single-block sequential decoding to multi-block parallel decoding by introducing code block identifier management. This allows the decoder to process multiple blocks simultaneously using the same clock frequency, thereby increasing productivity without the power consumption penalty associated with higher clock speeds.
3Productivity
If two parallel Viterbi decoders are used to achieve high-speed decoding, then decoding speed is improved, but manufacturing cost increases
Solution Approach 1:
The patent makes a single Viterbi decoder universal by enabling it to process multiple coded blocks through the coordination means. The shared memory and coordination logic allow the same hardware to perform multiple decoding functions sequentially and in parallel, replacing the need for multiple dedicated decoder units and reducing manufacturing costs.
Solution Approach 2:
The patent combines multiple decoding operations into one decoder unit, reducing the total hardware count and associated manufacturing costs. The coordination means manages the integration of multiple code block processing paths within a single decoder, achieving cost-effective high-speed decoding.
4Productivity
If clock frequency is increased to achieve high-speed decoding, then decoding speed is improved, but electromagnetic radiation increases
Solution Approach 1:
The patent segments the decoding workload into multiple independent coded blocks that can be processed in parallel within the same clock frequency. This segmentation allows the system to achieve higher effective processing speed without increasing the clock frequency, thereby avoiding the electromagnetic radiation issues associated with high-speed clocking.
Solution Approach 2:
The patent changes the processing approach from increasing clock frequency to increasing parallel processing capacity through code block management. This parameter change allows the system to achieve high-speed decoding while maintaining the same clock frequency, thus avoiding increased electromagnetic radiation.
Data Source
AI summary
A continuous parallel Viterbi decoder configured to (a) compute Trellis paths from an input bitstream encoded with a convolutional code, (b) backtrack the Trellis paths to generate an output signal, (c) store the Trellis paths in a shared memory, and (d) coordinate simultaneous read/write operations from and to the shared memory.