Parallelogram Semiconductor Layer for Low ON-Resistance
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing ON-resistance while maintaining the performance of gate electrode formation, as expanding the channel width to reduce resistance compromises the space available for forming the gate electrode.
Innovation Solution
The semiconductor device employs a parallelogram-shaped first semiconductor layer with oblique sides to increase the channel area, ensuring sufficient space for gate electrode formation and reducing ON-resistance, while maintaining the integrity of the gate electrode forming process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of the semiconductor layer is expanded to increase channel width, then the ON-resistance is reduced, but the space for forming the gate electrode becomes small, worsening the forming performance of the gate electrode
Solution Approach 1:
The semiconductor layer is designed with an asymmetric shape where the channel width varies along the channel length. Specifically, the semiconductor layer has a first width at one end and a second width at the other end, with the first width being greater than the second width. This asymmetric configuration allows the channel width to be expanded for lower ON-resistance while maintaining sufficient space for gate electrode formation at the narrower end.
Solution Approach 2:
Different regions of the semiconductor layer are assigned different widths to fulfill different functional requirements. The region with greater width provides lower resistance for current flow, while the region with smaller width ensures adequate spacing for gate electrode formation. This local variation in geometry optimizes both electrical performance and manufacturability.
2Reliability
If the channel width is increased to reduce ON-resistance, then the electrical characteristics are improved, but the available space for gate electrode formation is reduced
Solution Approach 1:
The semiconductor layer employs asymmetric geometry with varying width along its length. The channel width is maximized in regions where low resistance is critical, while the width is reduced in regions where gate electrode formation requires space. This creates an optimal balance between electrical performance and manufacturing feasibility.
Solution Approach 2:
Instead of uniformly increasing the channel width in one dimension, the invention varies the width along the length of the semiconductor layer, effectively using the longitudinal dimension to accommodate both wide and narrow sections. This dimensional approach allows simultaneous optimization of resistance and space for gate formation.
Data Source
AI summary
A semiconductor device according to the embodiment includes a plurality of semiconductor layers arranged along a first direction and a second direction, wherein each of the semiconductor layers includes a first semiconductor layer and second semiconductor layers positioned at both upper and lower sides of the first semiconductor layer, and a gate electrode which faces the first semiconductor layer. A row of the semiconductor layer in the first direction is oblique to a row of the semiconductor layer in the second direction. At least one part of peripheral faces of the first semiconductor layer is in contact with the gate electrode along the first direction.