Semiconductor Parasitic Capacitance Sensitivity Analysis
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Solution Overview
Problem
Manufacturing variability in semiconductor devices, particularly in contact structures, affects parasitic capacitance, leading to increased design Turn Around Time (TAT) and potential circuit malfunctions due to stricter timing verification conditions.
Innovation Solution
A sensitivity analysis system that calculates and analyzes the influence of manufacturing variability on parasitic capacitance by setting variations of parameters within a predetermined range, classifying them as main or sub-parameters for efficient extraction processing, and applying statistical relaxation to main parameters to exclude extreme scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manufacturing variability is considered in timing verification, then timing verification accuracy is improved, but design TAT increases
Solution Approach 1:
The patent segments parameters into main parameters (width, thickness of interconnection) and other parameters (thickness of interlayer insulating film). By focusing sensitivity analysis on main parameters that have the greatest impact on parasitic capacitance, the verification process becomes more efficient without sacrificing accuracy.
Solution Approach 2:
The patent applies statistical relaxation by changing how parameters are varied during verification. Instead of considering all parameters at extreme values simultaneously (which is statistically unrealistic), it relaxes the verification conditions to reflect more realistic manufacturing variability scenarios, thereby reducing unnecessary verification iterations.
2Reliability
If all parameters are varied to maximum extent simultaneously, then worst-case scenario coverage is improved, but design complexity increases
Solution Approach 1:
The patent changes the approach to parameter variation by applying statistical relaxation. It recognizes that simultaneous maximum variation of all parameters is statistically unrealistic and modifies the verification conditions to reflect more probable scenarios, thereby reducing verification complexity while maintaining reliability for realistic cases.
Solution Approach 2:
The patent applies different treatment to different parameters based on their sensitivity. Main parameters (interconnection width and thickness) are subjected to sensitivity analysis and statistical relaxation, while other parameters are handled differently. This localized approach reduces overall complexity while maintaining coverage of critical variations.
Data Source
AI summary
A sensitivity analysis system has a memory device in which an interconnect structure data indicating an interconnect structure included in a semiconductor device is stored. The interconnect structure has: a main interconnection; and a contact structure electrically connected to the main interconnection and extending toward a semiconductor substrate. Parameters contribute to parasitic capacitance of the interconnect structure, and variation of each parameter from a design value caused by manufacturing variability is represented within a predetermined range. The sensitivity analysis system further has: a parameter setting unit that sets the variation to a plurality of conditions within the predetermined range; a capacitance calculation unit that calculates the parasitic capacitance of the interconnect structure in each of the plurality of conditions; and a sensitivity analysis unit that analyzes, based on the calculated parasitic capacitance, response of the parasitic capacitance to variation of the each parameter.