Parasitic Extraction for Semiconductor Layouts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current parasitic extraction methods for semiconductors require repeated analysis at multiple corners (process, temperature, and voltage variations), leading to complexity and large storage needs, as they capture parasitic values for each corner individually rather than accounting for unique combinations of process and temperature corners.
Innovation Solution
A computer-implemented method that performs parasitic extraction with a single pass through the semiconductor layout, identifying unique process and temperature combinations, storing parasitic values in an array, and performing multi-corner analysis, which reduces complexity and storage requirements by capturing needed dimensions only once.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parasitic extraction is performed by analyzing the layout separately for each corner (process, temperature, voltage combinations), then complete parasitic values for all corners are obtained, but the analysis complexity and storage requirements increase significantly
Solution Approach 1:
The patent merges the extraction process for multiple corners into a single unified pass through the layout. Instead of performing separate extractions for each corner combination, the system extracts parasitic values once and uses process, temperature, and voltage corner tables to compute corner-specific values through mathematical relationships, thereby reducing analysis complexity while maintaining completeness
Solution Approach 2:
The extracted parasitic values are made universal by creating corner tables that define relationships between corners. A single set of extracted values serves multiple corners through scaling factors and mathematical transformations, allowing the same extraction data to be reused across different process, temperature, and voltage conditions
2Reliability
If parasitic values are stored for each corner individually, then all corner-specific parasitic data is available, but storage requirements become large
Solution Approach 1:
Instead of storing actual parasitic values for each corner, the patent creates corner tables that contain scaling factors, offset values, and mathematical relationships. These tables act as templates that can generate corner-specific parasitic values on-demand, dramatically reducing storage requirements while maintaining data availability
Solution Approach 2:
The patent transforms the storage approach from storing absolute parasitic values for each corner to storing parameter relationships (scaling factors, exponents, offsets) that define how parasitic values change across corners. This parameter-based approach reduces storage needs while preserving the ability to retrieve accurate corner-specific data
3Measurement precision
If repeated analysis is performed for multiple corners, then accurate corner-specific parasitic values are obtained, but computational resources and time are consumed
Solution Approach 1:
The patent performs preliminary extraction of parasitic values from the layout in a single pass, storing these base values and their relationships in corner tables. This preliminary action captures all necessary geometric and electrical information once, eliminating the need for repeated analysis while preserving accuracy for all corners
Solution Approach 2:
The patent replaces the mechanical process of repeated layout analysis with a computational approach using corner tables and mathematical relationships. Instead of re-analyzing the physical layout for each corner, the system uses algebraic transformations of the initially extracted values, substituting computational efficiency for repeated mechanical analysis
Data Source
AI summary
Parasitic extraction is a useful tool for analyzing and improving timing and other characteristics of semiconductor chips. Parasitic resistance and capacitance values are determined and stored in arrays. The parasitic values are extracted for multiple corners with a single analysis of the layout. Multi-corner analysis is performed using the parasitic values thereby optimizing the timing across various temperature and process operating points.