ESD Protection Apparatus with Epitaxial Layer Doping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Parasitic silicon controlled rectifiers (SCR) in semiconductor ESD protection circuits have high trigger voltages, which can delay protection and require additional components like field-planted diodes and diffusion resistors, increasing complexity and cost.
Innovation Solution
A semiconductor ESD protection apparatus with a substrate, doped wells, and epitaxial layers forming BJT equivalent circuits with different conductivity types, where epitaxial material with lower doping concentration increases resistance and carrier mobility, reducing trigger voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a parasitic SCR device is used in ESD protection circuits, then high current sinking/sourcing capability and low power dissipation are achieved, but high trigger voltage obstructs timely protection
Solution Approach 1:
The patent changes the doping concentration parameter of the epitaxial layer from high to low, which fundamentally alters the electrical characteristics of the SCR device. This parameter change reduces the trigger voltage from high to low levels, enabling timely ESD protection while maintaining the high current handling capability of the parasitic SCR structure.
Solution Approach 2:
The patent applies local quality by creating a specific low-doping concentration region in the epitaxial layer that is distinct from other regions of the semiconductor device. This localized modification of doping concentration in the epitaxial layer allows the SCR to have reduced trigger voltage specifically at the critical interface regions where triggering occurs, while other parts of the device maintain their original properties.
2Reliability
If secondary protection elements (field planted diode and diffusion resistor) are incorporated with lateral SCR device, then improved ESD protection is provided, but additional processing steps and production cost are required
Solution Approach 1:
The patent merges the ESD protection function into the intrinsic parasitic SCR structure itself by modifying the epitaxial layer doping concentration. This eliminates the need for separate secondary protection elements like field-planted diodes and diffusion resistors, as the SCR device itself becomes sufficiently protective through the epitaxial layer modification alone.
Solution Approach 2:
The patent enables the parasitic SCR device to serve its own protection function effectively by modifying its epitaxial layer structure. The low-doping concentration epitaxial layer allows the SCR to trigger at appropriate voltage levels without requiring external assistance from additional protection components, making the device self-sufficient for ESD protection.
3Reliability
If secondary protection elements are added to lateral SCR device, then ESD protection is improved, but layout size cannot be reduced
Solution Approach 1:
The patent combines the ESD protection functionality directly into the parasitic SCR device structure through epitaxial layer modification. This integration eliminates the need for separate protection elements that would occupy additional layout space, achieving effective ESD protection within the same footprint as the original SCR device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces trigger voltage of the parasitic SCR device, enhancing ESD protection, simplifying IC fabrication, and reducing layout size and manufacturing costs.
Implementation Method 1
epitaxial material with lower doping concentration increases resistance and carrier mobility, reducing trigger voltage
Data Source
AI summary
A semiconductor ESD protection apparatus comprises a substrate; a first doped well disposed in the substrate and having a first conductivity; a first doped area having the first conductivity disposed in the first doped well; a second doped area having a second conductivity disposed in the first doped well; and an epitaxial layer disposed in the substrate, wherein the epitaxial layer has a third doped area with the first conductivity and a fourth doped area with the second conductivity separated from each other. Whereby a first bipolar junction transistor (BJT) equivalent circuit is formed between the first doped area, the first doped well and the third doped area; a second BJT equivalent circuit is formed between the second doped area, the first doped well and the fourth doped area; and the first BJT equivalent circuit and the second BJT equivalent circuit have different majority carriers.