Parity Cell Region Adaptive ECC Storage for DRAM Yield
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Solution Overview
Problem
The increasing bit errors and reduced yield in DRAMs due to shrinking fabrication design rules necessitate more efficient use of the parity cell region in semiconductor memory devices, which is typically underutilized.
Innovation Solution
Incorporating an error correction code (ECC) engine and a control logic circuit that selectively uses the parity cell region for storing parity data generated based on main data, allowing adaptive ECC levels to be set according to the importance of the data, thereby increasing the usability of the parity cell region and reducing its size overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the fabrication design rule of DRAMs is shrunk to increase capacity, then the memory density is improved, but the bit errors increase and yield decreases
Solution Approach 1:
The patent applies preliminary action by generating and storing parity data before main data is written to the memory cell array. The ECC engine generates parity data in advance based on the main data to be stored, and this pre-generated parity data is stored in the parity cell region. When reading, the pre-stored parity data is immediately available for error correction, preventing bit errors that would otherwise occur due to the shrunk fabrication design rules.
2Reliability
If a parity cell region is allocated for error correction, then the reliability is improved, but the usable storage capacity is reduced
Solution Approach 1:
The patent applies universality by enabling the parity cell region to serve multiple functions. It can store parity data generated by the ECC engine for error correction, or it can store additional main data when error correction is not required. The control logic circuit dynamically switches between these functions based on the operational mode, allowing the same physical region to provide either reliability enhancement or increased storage capacity as needed.
3Reliability
If the parity cell region is used to store parity data, then the error correction capability is improved, but the size overhead increases
Solution Approach 1:
The patent applies dynamics by making the function of the parity cell region changeable rather than fixed. The control logic circuit dynamically configures the parity cell region to store either parity data or main data based on the operational requirements. This dynamic reconfiguration allows the system to reduce the effective size overhead of the parity cell region by utilizing it for main data storage when full error correction capability is not needed.
4Reliability
If ECC encoding and decoding operations are performed, then the bit error rate is reduced, but the operation complexity increases
Solution Approach 1:
The patent applies the taking out principle by extracting the ECC encoding and decoding operations into a dedicated ECC engine that is separate from the main memory array. This dedicated engine handles all error correction operations, simplifying the overall system architecture. The control logic circuit manages the interaction between the ECC engine and memory cell array, coordinating parity data generation and error correction in a systematic manner that reduces operational complexity.
Data Source
AI summary
A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.