Parity Check Unit for Semiconductor Memory Command Signal Error Detection
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Solution Overview
Problem
As semiconductor memory devices operate at higher speeds, the probability of signal errors increases, necessitating effective error checking mechanisms to ensure reliable operation, particularly in dynamic random access memory (DRAM) systems with finite data retention characteristics.
Innovation Solution
Incorporating a parity check unit that receives command and address signals, performs error checking, and outputs a parity indication signal, along with timing units that delay these signals and control the passage or blocking of commands based on parity error states, to prevent errors in memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operating speed of the semiconductor memory device is increased, then the productivity is improved, but the error probability of signals transmitted or received increases
Solution Approach 1:
The patent applies preliminary action by performing parity check operations on command signals and address signals before they are processed by the memory device. The parity check unit generates parity signals and checks for errors in advance, allowing the system to detect and correct potential signal transmission errors before they affect memory operations, thus maintaining reliability at high operating speeds
2Reliability
If a parity check unit is added to perform error checking, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent merges the parity check functionality into the existing command control logic unit of the memory device. The parity check unit is integrated alongside the command decoder and address decoder, sharing the same structural framework. This merging approach allows error checking to be performed without adding separate, independent complexity, as the parity check functions are combined with the existing signal processing paths
Data Source
AI summary
A semiconductor memory device comprising of a parity check unit configured to receive a command signal and a parity signal to perform error checking in the command signal and output a parity indication signal; a delay unit including a plurality of registers configured to time delay by n clock cycles the parity indication signal and output a delayed parity indication signal; a command register configured to time delay by n clock cycles the command signal and output a delayed command; and a decoder configured to pass or block the delayed command signal based on the delayed parity indicator signal.