Partial Block Erase for 3D Memory Using Wordline Isolation

Solution Overview

Problem

In three-dimensional (3D) memory devices, erasing a block is a time-consuming and power-intensive process that affects all wordlines, regardless of their state or end-of-life condition, leading to inefficient data storage and potential premature wearout.

Innovation Solution

Implementing a partial block erase method where sub-blocks within a 3D memory can be independently erased, using switches to electrically isolate wordlines nearing end-of-life, allowing for selective exclusion from erase operations, thereby reducing power consumption and extending the life of these components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a full block erase operation is performed on 3D memory, then all data in the block is erased, but the operation is time-consuming and power-intensive

Engineering Contradiction:

Improvedata erasure completenessVSAvoiderase operation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent divides a memory block into multiple independently erasable sub-blocks using physical segmentation structures (trenches, isolation regions, or dummy wordlines) that electrically isolate sub-blocks from each other. This allows selective erasure of only the necessary sub-blocks rather than the entire block, reducing erase time and power consumption while maintaining complete erasure reliability for the targeted portions.

Inventive Principle:

Principle #1Segmentation

2Reliability

If a full block erase operation is performed on 3D memory, then all data in the block is erased, but power consumption is excessive

Engineering Contradiction:

Improvedata erasure completenessVSAvoiderase operation power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent divides a memory block into multiple independently erasable sub-blocks using physical segmentation structures (trenches, isolation regions, or dummy wordlines) that electrically isolate sub-blocks from each other. This allows selective erasure of only the necessary sub-blocks rather than the entire block, reducing erase time and power consumption while maintaining complete erasure reliability for the targeted portions.

Inventive Principle:

Principle #1Segmentation

3Reliability

If erase operation is performed on all wordlines, then complete erasure is achieved, but wordlines nearing end-of-life are unnecessarily worn out

Engineering Contradiction:

Improveerase operation completenessVSAvoidwordline lifespan

Core Design Contradiction:

ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent divides a memory block into multiple independently erasable sub-blocks using physical segmentation structures (trenches, isolation regions, or dummy wordlines) that electrically isolate sub-blocks from each other. This allows selective erasure of only the necessary sub-blocks rather than the entire block, reducing erase time and power consumption while maintaining complete erasure reliability for the targeted portions.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different treatment to different regions of the memory block by identifying which sub-blocks contain data requiring erasure and which wordlines are approaching end-of-life conditions. The segmentation structures enable localized erasure operations that preserve healthy wordlines while erasing only the necessary regions, extending overall memory lifespan through selective maintenance.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS9286989B2Partial block erase for a three dimensional (3D) memory

Publication Date: 2016.03.15 SANDISK TECHNOLOGIES LLC

AI summary

A method includes, at a non-volatile memory having a three dimensional (3D) memory configuration, performing an erase operation. Performing the erase operation includes providing a first control signal to isolate a first portion of a string of the non-volatile memory from a second portion of the string. Performing the erase operation further includes providing a first erase signal to erase the second portion of the string while data is maintained at the first portion of the string.