Partial Block Erase Voltage Adjustment in Memory Devices
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Solution Overview
Problem
Existing memory devices face challenges in performing accurate erase operations on blocks with varying levels of programming, leading to potential memory degradation due to the use of higher pre-program voltages to equalize threshold voltage distributions.
Innovation Solution
The solution involves maintaining a constant pre-program voltage for all blocks and adjusting the erase verify voltage threshold based on the ratio of programmed to total pages in the block, thereby avoiding memory degradation and ensuring accurate erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If higher pre-program voltages are used to equalize threshold voltage distributions in blocks with varying programming levels, then erase operation accuracy is improved, but memory degradation occurs
Solution Approach 1:
The patent applies different verify voltage thresholds to different portions of memory blocks based on their programming status. Specifically, fully-programmed blocks use a first verify voltage threshold while partially-programmed blocks use a second verify voltage threshold. This local differentiation allows accurate erase verification without applying excessively high pre-program voltages that would cause memory degradation.
Solution Approach 2:
The patent changes the verify voltage threshold parameter based on the programming level of memory blocks. By dynamically adjusting the verify threshold according to whether blocks are fully or partially programmed, the system achieves accurate erase operations without requiring uniformly high pre-program voltages across all blocks, thereby preventing memory degradation.
2Device complexity
If uniform erase operations are applied to all blocks regardless of programming level, then device complexity is reduced, but erase operation accuracy deteriorates
Solution Approach 1:
The patent introduces dynamic adjustment of verify voltage thresholds based on block programming status. Rather than using a static uniform approach, the system adaptively selects between first and second verify voltage thresholds according to whether blocks are fully or partially programmed, achieving high erase accuracy without excessive complexity.
Solution Approach 2:
The patent implements a feedback mechanism where the erase verify operation uses different voltage thresholds based on detected programming levels of blocks. This feedback-driven approach allows the system to automatically adjust verification parameters to match actual block states, ensuring accurate erase operations while maintaining manageable device complexity.
Data Source
AI summary
Described are systems and methods for performing partial block erase operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying, in a memory device, a block comprising a plurality of memory cells; estimating, in the block, a number of pages having a predefined program state; determining, based on the number of pages having the predefined program state, an erase verify voltage to be applied to the block; causing an erase operation to be performed with respect to the block; and causing an erase verify operation to be performed, using the erase verify voltage, with respect to the block.