Partial Etching of Conductive Layers for Gate Dielectric Protection
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Solution Overview
Problem
In semiconductor device fabrication, the removal of hard mask layers can damage the gate dielectric layer, and the removal of photo resist can damage exposed dielectric or metal layers, leading to issues with gate leakage and capacitance in high-speed devices.
Innovation Solution
A method involving partial etching of conductive layers and hard mask layers, where a portion of the conductive layer or hard mask is protected during etching to prevent damage to underlying dielectric layers, allowing for the completion of semiconductor device formation without compromising gate dielectric integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the hard mask layer is completely removed after etching the first metal layer, then the second metal layer can be deposited, but the gate dielectric layer is damaged by exposure to removal chemistry
Solution Approach 1:
A second hard mask layer is deposited over the first hard mask layer before etching the first metal layer. This preliminary action ensures that when the first hard mask layer is removed, the gate dielectric layer remains protected by the second hard mask layer, preventing damage from removal chemistry while still allowing the etching and deposition processes to proceed
Solution Approach 2:
The second hard mask layer acts as an intermediary protective layer between the gate dielectric layer and the removal chemistry. It absorbs the harmful effects of the removal process, allowing the first hard mask layer to be completely removed without exposing the vulnerable gate dielectric layer to damaging chemicals
2Ease of operation
If photo resist is removed using standard chemistry, then the pattern is cleared, but exposed dielectric or metal layers are damaged
Solution Approach 1:
The hard mask layer serves as an intermediary protective barrier during photo resist removal. The hard mask layer remains in place to protect underlying dielectric and metal layers from damage by photo resist removal chemistry, while still allowing the photo resist to be completely removed to clear the pattern
3Reliability
If the gate dielectric layer is thinned to increase gate capacitance, then high-speed device performance improves, but leakage across the dielectric layer increases
Solution Approach 1:
The gate structure uses a composite dielectric system combining a thin first dielectric layer (for high capacitance) with a second thicker dielectric layer (for leakage reduction). This composite structure allows the device to achieve both high gate capacitance for speed and low leakage for reliability, resolving the contradiction between the two opposing requirements
Data Source
AI summary
A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so that said first portion of the conductive layer is removed. The method further includes completing formation of the semiconductor device.