Partial Integrated Heat Spreader for Multi-Chip Package Thermal Crosstalk
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Solution Overview
Problem
In multi-chip packages, the integration of a heat spreader that covers all IC dies can lead to poor thermal performance for thinner dies due to increased thermal resistance and thermal crosstalk between adjacent dies, where the thicker dies' heat dissipation can negatively impact thinner dies.
Innovation Solution
A partial integrated heat spreader is used, covering only the IC dies that require it, with a thermal interface material confined to the area over the primary IC die, eliminating the heat spreader and additional TIM layer from the thermal conduction path for satellite IC dies, thus reducing thermal resistance and crosstalk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a full integrated heat spreader covers all IC dies, then thermal management is improved for thicker dies, but thermal resistance increases and thermal crosstalk worsens for thinner dies
Solution Approach 1:
The heat spreader is segmented into two distinct parts: a first heat spreader portion covering the thicker IC die and a second heat spreader portion covering the thinner IC die. This segmentation allows each portion to be optimized independently for its respective die's thermal requirements, preventing thermal crosstalk while maintaining effective heat dissipation for both dies.
2Device complexity
If a single integrated heat spreader covers all dies, then package structure is simplified, but thermal crosstalk between adjacent dies increases
Solution Approach 1:
The heat spreader is divided into separate portions for different dies, with each portion independently managing heat for its associated die. This physical separation prevents thermal crosstalk between adjacent dies while maintaining a relatively simple package structure without requiring complex external thermal management systems.
3Stability of the object's composition
If thermal interface material thickness is increased to accommodate die height differences, then mechanical compliance is improved, but thermal resistance increases
Solution Approach 1:
The first thermal interface material layer is positioned only between the thicker IC die and the first heat spreader portion, while the second thermal interface material layer is positioned only between the thinner IC die and the second heat spreader portion. This localized arrangement allows each TIM layer to be optimized for its specific die's thickness requirements, maintaining mechanical compliance without unnecessarily increasing thermal resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances thermal performance by optimizing heat dissipation for each die individually, improving the overall thermal management of the multi-chip package without increasing package warp or stiffness requirements.
Implementation Method 1
a thermal interface material (TIM) portion 10A is between die 20 and IHS 40, with another TIM portion 10B between die 15 and IHS 40
Implementation Method 2
an integrated heat spreader integrated into a package may help to dissipate thermal load by improving heat transfer from a packaged IC die to an external heat sink
Implementation Method 3
improving heat transfer from a packaged IC die to an external heat sink
Data Source
AI summary
A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die.