Arithmetic Operation Device With Partial-Reconfiguration Test Partitioning
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Solution Overview
Problem
Existing methods for testing reconfigurable logic circuits in in-vehicle systems are inefficient and time-consuming, failing to meet the high reliability and speed requirements of autonomous driving systems.
Innovation Solution
A testing method utilizing a partially reconfigurable programmable logic unit that separates test target and non-test circuits through partial reconfiguration, employing a test partition unit to control and execute tests efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a self-testing circuit is formed by loading program data into memory to configure test circuits using programmable logic blocks, then the test can be executed, but the test time is excessively long
Solution Approach 1:
The invention divides the test target block into multiple sub-blocks (first test target sub-block and second test target sub-block) and creates separate self-testing circuits for each sub-block. This segmentation allows parallel testing of different circuit portions simultaneously, significantly reducing the overall test time while maintaining comprehensive coverage of the reconfigurable logic circuit.
Solution Approach 2:
The invention introduces a temporal dimension to the testing process by sequentially configuring different self-testing circuits in different time periods. In the first time period, a first self-testing circuit is configured to test the first test target sub-block, and in the second time period, a second self-testing circuit is configured to test the second test target sub-block. This time-based dimensionality enables efficient testing without requiring all test circuits to be simultaneously configured.
2Reliability
If full reconfiguration is performed to test the entire programmable logic device, then complete testing coverage is achieved, but the test time increases significantly
Solution Approach 1:
The invention applies partial reconfiguration by creating self-testing circuits only for the necessary test target blocks rather than reconfiguring the entire programmable logic device. The self-testing circuit is configured to test only the specific test target block (or sub-blocks) identified as needing testing, which reduces the reconfiguration scope and time while maintaining adequate testing coverage for the problematic areas.
Solution Approach 2:
The invention extracts the testing function from the general reconfigurable logic blocks and creates dedicated self-testing circuits specifically for testing purposes. These self-testing circuits are formed by loading test program data into memory and configuring test logic blocks that are solely responsible for testing the test target block, separating the testing function from the normal operational logic.
Data Source
AI summary
An arithmetic operation device executes a test using a partially reconfigurable programmable logic unit, the programmable logic unit includes a test target circuit which is a user circuit, and a non-test circuit which is a user circuit which is not the test target circuit, and the arithmetic operation device includes a configuration control unit which causes the programmable logic unit to form, by partial reconfiguration, a test partition unit which separates the test target circuit and the non-test circuit, and a partition control unit which controls the test partition unit to test the test target circuit.