Testing Circuit With Partitioned Clock Fan-Out for Lower IR Drop

The patent divides the large clock domain into multiple smaller fan-out partitions (first fan-out partition, second fan-out partition, etc.). Each partition can be independently controlled and activated. This segmentation allows the system to achieve comprehensive test coverage by activating different partitions sequentially or in combination, while avoiding the excessive IR drop that would occur if all partitions were activated simultaneously in a single large clock domain.

The patent implements dynamic control over the activation of different fan-out partitions using control signals (first control signal, second control signal, etc.). The clock gating mechanism allows partitions to be selectively enabled or disabled based on testing requirements, optimizing the balance between test coverage and power consumption/IR drop in real-time during the testing process.

By segmenting the clock domain into multiple fan-out partitions with independent control, the system can activate only the necessary partitions for each specific test scenario rather than all partitions simultaneously. This reduces peak power consumption during scan capture operations while still achieving comprehensive test coverage across different testing phases.

The patent applies partial action by activating only the required fan-out partitions based on specific testing needs rather than all partitions at once. The control circuit selectively enables partitions using one-hot encoded control signals, ensuring sufficient test coverage is achieved with minimal power consumption by activating only the necessary subset of partitions for each test case.