Partitioned DRAM Row Access for Power Savings
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Solution Overview
Problem
Current DRAM architectures consume significant power due to the need to activate entire rows of access devices during memory access, even when not all partitions are used, leading to inefficiencies in power usage, especially in applications with random access patterns that do not benefit from deep page accesses.
Innovation Solution
The DRAM array is partitioned using multiple word lines per row, allowing only the necessary partitions to be activated, with address decoder logic determining which partitions to access, thereby reducing power consumption without affecting data availability or increasing recovery time from a dormant state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the entire row of access devices is activated during memory access, then all partitions within the row can be accessed, but power consumption increases significantly
Solution Approach 1:
The row of access devices is divided into multiple independently controllable partitions using separate word lines for each partition. This segmentation allows the system to activate only the specific partition containing the target data rather than the entire row, thereby reducing power consumption while maintaining full access capability to all partitions when needed.
2Use of energy by moving object
If multiple word lines are used to partition the row, then power consumption is reduced by activating only necessary partitions, but device complexity increases
Solution Approach 1:
The row is segmented into partitions with dedicated word lines, enabling selective activation. The complexity increase is managed by organizing the segmented structure in a regular, predictable pattern that simplifies control logic and address decoding.
Solution Approach 2:
The system dynamically selects which word lines to activate based on the specific memory access requirements. This dynamic control allows the complexity of multiple word lines to be managed efficiently, as only the necessary subset is active at any given time rather than all word lines being permanently complex.
3Productivity
If deep page accesses are implemented for large page sizes, then performance is improved for certain applications, but power consumption increases due to activating many row devices
Solution Approach 1:
By segmenting the row into partitions with independent word line control, the system can maintain deep page access performance for applications that need it while avoiding the activation of unnecessary access devices. The segmentation allows precise control over which devices are activated based on the actual access pattern.
Solution Approach 2:
The system performs partial activation of row devices by activating only the specific partition needed for the current access operation. This partial action maintains performance for required accesses while avoiding the excessive power consumption of activating the entire row, especially beneficial for random access patterns where full row activation is unnecessary.
Data Source
AI summary
A random access memory device includes an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Address decoder logic in signal communication with the array is configured to receive a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated.