Partitioned Package Substrate for Large-Die Warpage Control
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Solution Overview
Problem
Semiconductor design companies face challenges in chip design complexity and high costs due to low production yield and warpage issues in large-die ASIC packages, especially in advanced packaging technologies like 7 nm, 5 nm, and 3 nm geometries.
Innovation Solution
A semiconductor package using substrate block integration (SBI) with a partitioned package substrate composed of discrete substrates arranged side-by-side, connected by conductive elements and adjoined with a gap-filling adhesive, featuring a central substrate and peripheral substrates, and optionally including passive circuit elements and a mold cap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a large-die ASIC package is used to meet networking data center demands, then the package size increases to accommodate larger dies, but the production yield decreases and cost increases due to low substrate yield at large sizes
Solution Approach 1:
The package substrate is divided into multiple smaller substrate blocks (first substrate block, second substrate block, third substrate block, fourth substrate block) arranged in a 2x2 configuration. Each substrate block has dimensions smaller than a single large substrate, allowing them to be manufactured with higher yield. The substrate blocks are interconnected through bridge structures to function as a unified large package substrate, effectively achieving segmentation to resolve the contradiction between large package area and production yield.
2Area of moving object
If a large-die ASIC package is used to accommodate bigger chips, then the die size increases to meet performance requirements, but warpage problems occur due to thermal and mechanical stress in large substrates
Solution Approach 1:
The large package substrate is segmented into multiple smaller substrate blocks, each with reduced dimensions that minimize thermal and mechanical stress accumulation. This segmentation prevents the warpage issues inherent in large monolithic substrates while still providing the necessary large area for big-die ASIC packaging through the combined arrangement of multiple blocks.
Solution Approach 2:
Different substrate blocks can be designed with locally optimized properties suitable for their specific functions. The bridge structures connecting the substrate blocks are designed with specific mechanical and thermal properties to accommodate differential expansion and contraction, allowing each local region to have the quality needed for its particular role in reducing overall warpage.
3Area of moving object
If advanced packaging is adopted to shrink different functions onto ASIC, then integration density increases to reduce area, but device complexity increases making the process more complex and expensive
Solution Approach 1:
The packaging structure is segmented into modular substrate blocks that can be independently manufactured and then assembled. This modular approach reduces complexity by breaking down the complex single-substrate manufacturing process into simpler, repeatable steps for each block, followed by standardized assembly procedures using support pillars and bridge structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves reliability, design flexibility, and reduces production costs while addressing warpage issues, enhancing the performance of large-die semiconductor packages.
Implementation Method 1
the discrete substrates are adjoined together by using an adhesive that fills into the gap
Implementation Method 2
A plurality of solder balls is mounted on a second surface of the partitioned package substrate opposite to the first surface
Implementation Method 3
the conductive elements comprise micro-bumps, copper bumps or copper pillars
Data Source
AI summary
A semiconductor package includes a partitioned package substrate that is composed of multiple discrete substrates arranged in a side-by-side manner. The discrete substrates include a central substrate and peripheral substrates surrounding the central substrate. At least one integrated circuit die is mounted on a first surface of the partitioned package substrate. A plurality of solder balls is mounted on a second surface of the partitioned package substrate opposite to the first surface.