Parylene-Coated Die Carrier for Ion Protection and Via Alignment

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Solution Overview

Problem

Existing methods for embedding medium and high-voltage chip-carrier subassemblies like MOSFET or IGBT devices face challenges in handling stability, ion protection, and alignment during processing, leading to increased costs and compatibility issues with existing processing steps.

Innovation Solution

A semiconductor device with a parylene coating covering the semiconductor die and carrier surfaces, allowing for improved mechanical, environmental, and short-circuit protection, while maintaining visibility of chip features and compatibility with existing processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a mold-capping is applied to protect semiconductor dies, then protection against ion-migration and mechanical damage is improved, but alignment visibility for laser via drilling deteriorates and production complexity increases

Engineering Contradiction:
Improveprotection against ion-migrationVSAvoidalignment for laser via drilling
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The parylene coating is applied after die attachment but before via drilling, maintaining alignment visibility during critical processing steps while providing protection for subsequent handling and testing operations

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A thin parylene film coating provides ion-migration protection and mechanical protection without the thickness and opacity of mold-capping, allowing laser alignment while delivering protective functionality

Inventive Principle:
Principle #30Flexible shells and thin films

2Reliability

If a mold-capping is applied to protect semiconductor dies, then protection against ion-migration is improved, but device complexity and production cost increase

Engineering Contradiction:
Improveprotection against ion-migrationVSAvoidproduction process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The parylene coating provides a simple, uniform protective layer that can be applied in a single conformal deposition process, replacing the complex multi-step mold-capping process while maintaining ion-migration protection

Inventive Principle:
Principle #30Flexible shells and thin films

Solution Approach 2:

Changing from thick mold-capping material to thin parylene coating alters the protective layer parameters, achieving equivalent or superior protection with simplified processing and reduced production steps

Inventive Principle:
Principle #35Parameter changes

3Strength

If a mold-capping is applied to protect semiconductor dies, then mechanical protection is improved, but handling stability during processing deteriorates

Engineering Contradiction:
Improvemechanical protectionVSAvoidhandling stability
Core Design Contradiction:
StrengthVSStability of the object's composition

Solution Approach 1:

The thin parylene film provides mechanical protection without adding significant mass or altering the mechanical properties of the semiconductor device, maintaining handling stability during processing operations

Inventive Principle:
Principle #30Flexible shells and thin films

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The parylene coating provides enhanced mechanical and ion-barrier protection, reduces production effort, and maintains alignment visibility, thereby reducing costs and improving handling stability without altering existing production processes.

Implementation Method 1

a parylene coating covering at least portions of the surfaces of the semiconductor die and/or the carrier

Methodology Applied
Scientific EffectParylene coating: Parylene

Data Source

PatentUS12588546B2Semiconductor device comprising a semiconductor die and a carrier both covered by a parylene coating
Publication Date: 2026.03.24 INFINEON TECHNOLOGIES AG
  • US12588546B2 patent drawing
  • US12588546B2 patent drawing
  • US12588546B2 patent drawing

AI summary

A semiconductor device includes a carrier comprising a recess, a semiconductor die disposed in the recess, and a parylene coating covering at least portions of the surfaces of the semiconductor die and the carrier.