Physical-Aware ECO Flow for Timing Closure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing VLSI design flow faces challenges in closing timing gaps between the implementation and sign-off stages due to differences in timing analysis results, requiring lengthy Engineering Change Order (ECO) flows with limited optimization capabilities, as physical layout information is not available during optimization, leading to multiple iterations and full circuit timing analysis.
Innovation Solution
A Physical-Aware Scope-based Sign-off (PASS) ECO flow that determines the timing scope associated with critical paths, incorporating physical information like route and placement data to perform targeted optimization moves, allowing for both logical and physical fixes within a smaller scope, thereby reducing the need for full circuit analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full circuit timing analysis is performed during ECO to ensure accurate timing results, then timing analysis accuracy is improved, but processing time increases significantly
Solution Approach 1:
The patent segments the full circuit into a reduced timing scope that includes only the critical path and affected logic cones. This segmentation allows timing analysis to focus only on relevant portions of the circuit, maintaining accuracy for timing-critical areas while avoiding unnecessary analysis of unrelated circuit sections, thus resolving the contradiction between comprehensive timing analysis accuracy and processing time.
Solution Approach 2:
The patent applies different analysis depths to different parts of the circuit. Full timing analysis is performed on the reduced timing scope (critical path and affected areas), while the rest of the circuit is excluded from intensive analysis. This local quality approach ensures timing accuracy where it matters most while significantly reducing overall processing time.
2Manufacturing precision
If physical layout information is incorporated during optimization, then optimization effectiveness is improved, but complexity of the optimization process increases
Solution Approach 1:
The patent performs preliminary actions by determining the reduced timing scope and identifying the critical path before performing optimization. Physical layout information is pre-processed to identify affected logic cones and critical paths, allowing the optimization process to focus only on relevant areas. This preliminary action reduces the complexity of the optimization process while maintaining high effectiveness by using physical information strategically.
3Manufacturing precision
If multiple iterations of full timing analysis are performed to close timing gaps, then timing closure accuracy is improved, but total processing time increases
Solution Approach 1:
The patent segments the timing analysis to focus only on the reduced timing scope (critical path and affected logic cones) during each iteration. By dividing the full circuit analysis into focused segments, multiple iterations can be performed to achieve timing closure without the prohibitive time cost of analyzing the entire circuit repeatedly, thus maintaining timing closure accuracy while reducing total processing time.
4Productivity
If simple optimization techniques are used during ECO, then processing speed is improved, but optimization capability is limited
Solution Approach 1:
The patent enhances optimization capability by applying physical-aware optimization techniques specifically to the reduced timing scope, while maintaining fast processing through focused analysis. The optimization engine can apply sophisticated techniques such as buffer insertion, logic restructuring, and routing adjustments, but only to the critical path and affected logic cones, not the entire circuit. This local quality approach provides advanced optimization capability where needed while maintaining overall processing speed.
Data Source
AI summary
Modifying a circuit includes: obtaining timing information of the circuit, wherein the timing information includes timing information pertaining to a critical path of the circuit; determining a scope associated with the critical path, the scope including a subset of the circuit; and performing a fix based at least in part on physical information associated with the circuit to improve timing of the scope.