Pass-Through Clock Traces for Stacked Dies With Lower Signal Skew
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices face signal integrity limitations due to increased loading and noise in clock signals as bandwidth increases, particularly exacerbated by longer clock traces used to provide clock signals to multiple dies in a semiconductor device package, leading to errors such as skew errors.
Innovation Solution
The implementation of pass-through clock traces in dual die package (DDP) semiconductor packages, which reduce the load on clock signals by eliminating branches or stubs, allowing clock signals to propagate directly between a printed circuit board (PCB) and semiconductor dies without termination, thereby maintaining signal integrity even at higher data transfer rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock traces with branches or stubs are used to provide clock signals to multiple dies, then the clock signal can reach multiple destinations, but the loading increases and signal integrity deteriorates due to reflections and noise
Solution Approach 1:
The clock trace is segmented into separate dedicated traces for each die, eliminating the need for branches or stubs. Each die receives its own direct clock trace from the PCB, which reduces signal loading and eliminates reflections caused by impedance mismatches at branch points.
Solution Approach 2:
The patent transitions from a planar clock distribution network with branches to a three-dimensional stacked architecture where multiple dies are vertically arranged. This allows each die to have its own dedicated clock trace path, eliminating the need for horizontal branching and reducing signal interference.
2Productivity
If longer clock traces are used to reach multiple dies, then more dies can be clocked, but signal noise and skew errors increase
Solution Approach 1:
By stacking dies vertically in the Z-dimension rather than arranging them horizontally in the XY-plane, the patent reduces the lateral distance clock traces must travel. Each die in the stack receives a clock signal through a relatively short vertical trace, minimizing signal degradation while still enabling multiple dies to be clocked.
Solution Approach 2:
Each die position in the stack is provided with locally optimized clock trace routing that accounts for the specific signal path length and impedance characteristics. This allows each local connection to be tuned for optimal signal quality rather than using a single long trace for all dies.
3Productivity
If additional clocks are added to maintain signal integrity at higher data transfer rates, then bandwidth increases, but device complexity and cost increase
Solution Approach 1:
The patent changes the physical parameters of the clock trace system - specifically the trace length, trace geometry, and impedance matching - to maintain signal integrity at existing clock frequencies. This allows the system to achieve higher effective data transfer rates through improved signal quality rather than by increasing clock frequency or adding more clocks.
Data Source
AI summary
Semiconductor packages with pass-through clock traces and associated devices, systems, and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate including a first surface having a plurality of substrate contacts, a first semiconductor die having a lower surface attached to the first surface of the package substrate, and a second semiconductor die stacked on top of the first semiconductor die. The first semiconductor die includes an upper surface including a first conductive contact, and the second semiconductor die includes a second conductive contact. A first electrical connector electrically couples a first one of the plurality of substrate contacts to the first and second conductive contacts, and a second electrical connector electrically couples a second one of the plurality of substrate contacts to the first and second conductive contacts.