Pass-through Interconnects for Microelectronic Dies
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Solution Overview
Problem
Conventional 3D interconnects in microelectronic die packages face challenges in reducing volume while increasing capacity, as they require dummy pads or difficult alignment, which occupy valuable die surface area and risk damaging integrated circuits.
Innovation Solution
The implementation of pass-through 3D interconnects that extend through substrate pads without making electrical contact with integrated circuits, using dielectric layers to isolate them, allowing for efficient electrical coupling between dies without occupying additional surface area and avoiding damage to sensitive oxide layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 3D interconnects are used to increase capacity, then die surface area is occupied by dummy pads, but this reduces the available area for functional circuits
Solution Approach 1:
The patent removes the dummy pad requirement by extracting the harmful element (dummy pads) from the system. Through-silicon vias are implemented that pass through the substrate without requiring additional bonding pads, thereby eliminating the occupation of valuable die surface area while maintaining the capacity enhancement goal.
Solution Approach 2:
The patent transitions from 2D surface-level interconnections to 3D through-substrate interconnections. By routing vias vertically through the entire substrate thickness, the design moves the interconnect path into the third dimension, eliminating the need for surface-area-consuming dummy pads and enabling higher density.
2Quantity of substance
If conventional 3D interconnects are used to increase capacity, then alignment precision is required, but this increases manufacturing difficulty and risk of damage
Solution Approach 1:
The patent introduces an intermediary approach where the through-substrate via structure itself serves as the alignment reference. By designing the via path to pass through the substrate without requiring precise alignment with external bonding pads, the system eliminates the stringent alignment precision requirements while achieving the desired capacity increase.
3Reliability
If conventional 3D interconnects make electrical contact with integrated circuits, then electrical connectivity is achieved, but this risks damaging sensitive oxide layers
Solution Approach 1:
The patent extracts the harmful interaction between interconnects and sensitive oxide layers by routing the through-substrate vias to pass through regions that avoid direct contact with integrated circuit structures. This eliminates the damage risk while maintaining electrical connectivity functionality.
Solution Approach 2:
The substrate itself acts as an intermediary that isolates the through-vias from the sensitive integrated circuits. The via structure passes through the substrate without making electrical contact with the circuits, thereby mediating the connection while protecting the oxide layers from damage.
Data Source
AI summary
Pass-through interconnect structures for microelectronic dies and associated systems and methods are disclosed herein. In one embodiment, a microelectronic die assembly includes a support substrate, a first microelectronic die positioned at least partially over the support substrate, and a second microelectronic die positioned at least partially over the first die. The first die includes a semiconductor substrate, a conductive trace extending over a portion of the semiconductor substrate, a substrate pad between the trace and the portion of the semiconductor substrate, and a through-silicon via (TSV) extending through the trace, the substrate pad, and the portion of the semiconductor substrate. The second die is electrically coupled to the support substrate via a conductive path that includes the TSV.