Pass Transistor Array for Nonvolatile Memory Area Reduction
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Solution Overview
Problem
Existing nonvolatile memory devices face challenges in reducing the size of pass transistors while maintaining high voltage capabilities, leading to increased chip area occupation and interference between block word lines and pass transistors.
Innovation Solution
The design incorporates a pass transistor array with high voltage transistors, including one common drain and two sources formed in one active region, allowing for efficient transmission of drive signals to multiple memory blocks, and forms pass transistors on both sides of memory blocks to minimize chip area occupation and reduce interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If pass transistor size is reduced, then chip area occupation decreases, but high voltage capability is compromised
Solution Approach 1:
The patent merges two pass transistors into a single active region, creating a shared structure where one active region supports two pass transistors. This consolidation reduces the total area occupied by pass transistors while maintaining the high voltage capability through shared drain and source connections, resolving the contradiction between area reduction and voltage capability preservation.
Solution Approach 2:
The shared active region serves multiple functions by supporting two pass transistors simultaneously. The common drain and source structures provide universal connection points that enable both pass transistors to operate with high voltage capability while occupying reduced area, as the infrastructure is shared rather than duplicated.
2Area of stationary object
If pass transistor density is increased, then chip area occupation decreases, but interference between block word lines and pass transistors increases
Solution Approach 1:
By merging two pass transistors into one active region, the patent reduces the number of discrete transistor structures, thereby reducing the sources of interference. The consolidated structure minimizes the electromagnetic interference between block word lines and pass transistors while achieving higher density and reduced chip area occupation.
3Ease of manufacture
If traditional pass transistor layout is used, then manufacturing is simpler, but layout flexibility is limited
Solution Approach 1:
The merged pass transistor structure maintains manufacturing simplicity by using standard active region formation processes while significantly improving layout flexibility. The shared active region can be positioned and configured more adaptably in the layout, allowing designers to optimize for various routing and placement requirements without complicating the manufacturing process.
Data Source
AI summary
A nonvolatile memory device includes a plurality of memory blocks, and a pass transistor array transmitting a plurality of drive signals to a selected memory block among the plurality of memory blocks in response to a block select signal. The pass transistor array includes high voltage transistors including one common drain and two sources formed in one active region and one of the plurality of drive signals transmitted to the common drain is transmitted to different memory blocks through the two sources.