Nonvolatile Memory Pass Transistor Voltage Adjustment
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Solution Overview
Problem
The performance of nonvolatile memory devices, particularly in three-dimensional structures like vertical NAND memory devices, is degraded due to increased integration and memory capacity, leading to inefficiencies in program, erase, and read operations.
Innovation Solution
A nonvolatile memory device with a control circuit that adjusts the level of high voltage applied to pass transistors during program, erase, and read operations based on program/erase cycle information and operating temperature, optimizing voltage differences and levels to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high voltage is applied to pass transistor gates during program operation, then program speed is improved, but power consumption increases and threshold voltage distribution degrades
Solution Approach 1:
The patent applies dynamic voltage adjustment by changing the high voltage level applied to pass transistor gates based on the program loop iteration. The voltage starts at a higher level for initial programming cycles and is gradually reduced in subsequent loops. This dynamic adjustment maintains fast programming speed in early loops while reducing power consumption and threshold voltage degradation in later loops, resolving the contradiction between speed and energy use.
2Speed
If high voltage is applied to pass transistor gates during erase operation, then erase speed is improved, but device reliability deteriorates due to increased stress
Solution Approach 1:
The patent implements periodic action by dividing the erase operation into multiple loops with varying voltage levels. Different high voltage levels are applied in different erase loops, allowing the system to achieve fast erase speed when needed while periodically reducing voltage stress to maintain device reliability. This periodic variation in voltage application resolves the contradiction between erase speed and device reliability.
3Measurement precision
If high voltage is applied to pass transistor gates during read operation, then read accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies parameter changes by adjusting the high voltage level applied to pass transistor gates during read operations based on operating conditions such as temperature and read loop number. By dynamically changing the voltage parameter, the system achieves high read accuracy when required while reducing power consumption under normal conditions, effectively resolving the contradiction between measurement precision and energy use.
4Ease of manufacture
If fixed high voltage level is used in all program loops, then manufacturing simplicity is maintained, but performance degrades due to threshold voltage distribution issues
Solution Approach 1:
The patent implements dynamic voltage adjustment across program loops, where the high voltage level applied to pass transistor gates varies based on the loop iteration number. This dynamic approach improves threshold voltage distribution by using higher voltages in early loops and lower voltages in later loops, while adding only moderate complexity to the control circuitry, thus resolving the contradiction between manufacturing simplicity and manufacturing precision.
Data Source
AI summary
A nonvolatile memory device includes a memory block and a control circuit. The memory block includes a plurality of cell strings where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction between a bit-line and a common source line. The control circuit adjusts a level of a high voltage applied to a gate of a pass transistor of a selected word-line such that a voltage difference between the high voltage and a program voltage applied to a drain of the pass transistor differs in at least a portion of a plurality of program loops based on a comparison of a number of the program loops and a reference number during a program operation on a target memory cells.