Passive Carrier Device Delivery for High-Volume Semiconductor Test
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Solution Overview
Problem
Conventional Automated Test Equipment (ATE) systems face challenges such as difficulty in maintaining signal fidelity and high-speed signal path calibration due to frequent disconnections, limited parallelism and high-volume manufacturing capabilities, and low utilization of expensive pick-and-place assemblies.
Innovation Solution
A slot-based ATE system utilizing multi-device passive carriers to transport semiconductor devices from the loading/unloading station to the test slots, eliminating the need to move test sockets and/or test circuitry, which simplifies the system design and enhances performance, reliability, and cost-effectiveness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Tester Interface Boards (TIBs) with sockets and active test circuitry are used to transport DUTs, then device testing capability is integrated into the transport mechanism, but high-frequency signal path calibration becomes difficult due to repeated disconnections and maintenance costs increase
Solution Approach 1:
The system separates the transport function (passive carrier) from the testing function (fixed test slots with sockets). The carrier holds multiple DUTs and transports them to test slots, while the test circuitry remains stationary. This segmentation eliminates repeated disconnections of high-frequency signal paths, maintaining signal fidelity while preserving device testing capability.
Solution Approach 2:
A passive carrier acts as an intermediary between the DUTs and the fixed test slots. The carrier transports DUTs to the test slots without requiring the test circuitry to move or disconnect, thereby maintaining continuous high-frequency signal paths while enabling device testing.
2Device complexity
If a centralized pick-and-place assembly is used to transfer DUTs between JEDEC trays and test sockets, then mechanical components are minimized, but parallelism and Units Per Hour (UPH) are severely limited
Solution Approach 1:
The system transitions from a single centralized pick-and-place assembly operating in one dimension to multiple test slots arranged in parallel, enabling simultaneous testing of multiple DUTs. This dimensional expansion from serial to parallel processing dramatically increases UPH while maintaining minimal mechanical complexity through the use of passive carriers.
3Productivity
If per-slot pick-and-place assemblies are used to transfer DUTs, then parallelism is increased, but system cost increases and utilization is low when test time is long
Solution Approach 1:
The passive carrier is self-sufficient, holding and transporting multiple DUTs to the test slots without requiring active manipulation mechanisms at each slot. This eliminates the need for expensive per-slot pick-and-place assemblies while maintaining parallelism, as the carrier can be loaded once and service multiple test slots sequentially or in parallel.
4Adaptability or versatility
If test sockets and test circuitry are moved with devices between loading/unloading station and test slots, then device transport is integrated, but signal fidelity deteriorates due to repeated disconnections
Solution Approach 1:
Instead of moving the test circuitry with the devices, the system inverts the approach by keeping the test circuitry fixed and moving only the passive carrier with DUTs. This inversion maintains continuous high-frequency signal paths at the fixed test slots while achieving device transport integration through the movable carrier.
Data Source
AI summary
A testing apparatus comprises a tester comprising a plurality of racks, wherein each rack comprises a plurality of slots, wherein each slot comprises: (a) an interface board affixed in a slot of a rack, wherein the interface board comprises test circuitry and a plurality of sockets, each socket operable to receive a device under test (DUT); and (b) a carrier comprising an array of DUTs, wherein the carrier is operable to displace into the slot of the rack, and wherein each DUT in the array of DUTs aligns with a respective socket of the plurality of sockets on the interface board. The testing apparatus further comprises a pick-and-place mechanism for loading the array of DUTs into the carrier and an elevator for transporting the carrier to the slot of the rack.