Integrated Passive Flip Chip Package with TSVs
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Solution Overview
Problem
Conventional IC packaging methods face limitations in integrating passive components, leading to larger footprints, higher costs, and longer signal paths due to direct contact and wire bonding, which are not suitable for the smaller form factors required by evolving mobile devices.
Innovation Solution
The integration of through-silicon vias (TSVs) with solderable underbump metalizations and surface mount passive devices mounted on the IC die, coupled to TSVs, and encapsulated with a molding compound to expose leadframe leads for complex electrical connections, allowing for compact and efficient packaging of ICs with passive components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If passive components are mounted on PCB leads with wire bonding, then electrical connection is achieved, but footprint area increases and signal path length increases
Solution Approach 1:
The patent merges the passive component directly with the IC die by mounting it on the die surface and establishing electrical connection through TSVs that pass through the die substrate. This integration eliminates the need for separate PCB mounting and wire bonding, thereby reducing the overall footprint area while maintaining reliable electrical connection.
Solution Approach 2:
The patent utilizes the vertical dimension by employing through-silicon vias (TSVs) that extend through the die substrate. This allows electrical connection to be established in the vertical direction rather than through horizontal wire bonds, reducing the horizontal footprint area while maintaining electrical connectivity.
2Reliability
If passive components are mounted on PCB leads with wire bonding, then electrical connection is achieved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple functions (passive component mounting and electrical connection) into a single integration process on the IC die. This eliminates the need for separate wire bonding and PCB mounting steps, reducing manufacturing complexity and cost while maintaining reliable electrical connection.
Solution Approach 2:
The passive component is mounted on the IC die during the semiconductor fabrication process itself, before final packaging. This preliminary integration allows for more efficient manufacturing workflows and reduces the need for subsequent assembly steps, thereby lowering overall package cost.
3Reliability
If passive components are mounted on PCB leads with wire bonding, then electrical connection is achieved, but signal path length increases causing energy loss
Solution Approach 1:
The patent merges the passive component directly with the IC die structure, placing it in immediate proximity to the active circuits. This integration dramatically shortens the signal path length compared to external PCB mounting, thereby reducing energy loss while maintaining reliable electrical connection through TSVs.
Solution Approach 2:
By using TSVs to establish vertical electrical connections through the die substrate, the patent creates a compact three-dimensional signal path. This vertical routing approach significantly reduces the horizontal signal path length and associated energy loss compared to traditional wire bonding methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables smaller, cost-effective, and more efficient packaging of ICs with passive components by reducing the footprint and signal path length, addressing the limitations of conventional methods.
Implementation Method 1
at least one pair of through silicon via (TSV)s, the TSVs having a first end and a second end, wherein the first end of the each TSV is coupled to the metal interconnection patterns of the active surface of the integrated circuit die and the second end of the TSV is coplanar with the back surface of the integrated circuit die
Implementation Method 2
The first set of bond pads of the plurality of bond pads are coupled to leads of the lead frame by solder balls; Each TSV has solderable under bump metalizations UBM on each end of the TSV
Implementation Method 3
molding compound encapsulating the assembly, wherein the molding compound protects the assembly from the outside environment while exposing the leads of the leadframe
Data Source
AI summary
A method for packaging integrated circuit die such that each package includes die with integrated passive components mounted to either the back surface, the active surface or both the back and active surfaces of the die.