Multi-Level Passive Element Memory Cell Read Circuit
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Solution Overview
Problem
In three-dimensional passive element memory arrays, reading and writing multi-level memory cells require multiple cycles, leading to performance penalties due to the need for multiple write and read operations and the limitations of these arrays.
Innovation Solution
The implementation of a memory array with multi-level passive element memory cells that utilize a bit line biasing circuit and a word line biasing circuit to generate signals indicative of current levels, allowing for the discrimination between memory cell states using different combinations of reference current levels and read bias voltages, thereby reducing the number of read cycles required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional sensing at three exponentially stepped current levels is used to distinguish between four states, then measurement precision is improved, but read cycle time increases due to multiple stabilization delays
Solution Approach 1:
The patent segments the state discrimination process into two independent parts: LSB reading using a mid-level reference current, and MSB reading using first and second reference currents. This allows the LSB to be read first and stored, then the MSB is read using different reference currents without requiring sequential stabilization for all four states, thereby reducing total read cycle time while maintaining measurement precision.
Solution Approach 2:
The patent applies preliminary action by reading the LSB first and storing it in a register before reading the MSB. The LSB reading uses a mid-level reference current that can be stabilized independently. Once the LSB is captured, the system transitions to reading the MSB using different reference currents, eliminating the need to wait for complete stabilization of all current levels before making any state determination.
2Manufacturing precision
If multiple write cycles are used to program multi-level memory cells, then manufacturing precision is improved, but productivity deteriorates due to increased write time
Solution Approach 1:
The patent employs dynamic programming where the programming voltage is adjusted based on the current resistance state of the memory cell. The system dynamically selects between different programming voltages (first programming voltage for lower resistance states, second programming voltage for higher resistance states) to achieve precise multi-level programming in fewer cycles, thereby improving both accuracy and speed.
3Quantity of substance
If bit line is highly capacitively loaded to store multiple states, then memory density is improved, but read cycle time increases due to stabilization delays
Solution Approach 1:
The patent segments the reading operation into two phases: first reading the LSB using a mid-level reference current, then reading the MSB using different reference currents. This segmentation allows the highly capacitive bit line to be read in stages rather than requiring complete stabilization before any reading occurs, thereby maintaining high memory density while reducing the effective read cycle time.
Solution Approach 2:
The patent applies preliminary action by performing the LSB reading first while the bit line is still stabilizing, and storing this information before completing the full stabilization process. This allows the system to exploit the initial reading opportunity before the capacitive load fully stabilizes, reducing the effective read time despite the high capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient reading of multi-level passive element memory cell arrays by reducing the number of read cycles needed, improving performance by allowing for the determination of all four data states with only a single stabilization of the bit line voltage, thus enhancing the speed and efficiency of data retrieval.
Implementation Method 1
four memory cell states corresponding respectively to first, second, third, and fourth decreasing resistance levels
Implementation Method 2
a bit line biasing circuit configured to bias a selected bit line with a read bias voltage
Data Source
AI summary
A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.