Patterned Annealed Contact Structures for Semiconductor Devices
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Solution Overview
Problem
Semiconductor devices, particularly those made from wide bandgap materials like silicon carbide, are prone to breaking or cracking due to handling stresses and thermomechanical stresses during fabrication and reliability testing, which increases with larger device areas.
Innovation Solution
The implementation of annealed metal silicide contact structures with patterns that are nonparallel to the fracture planes and peripheral edges of the substrate, reducing exposure to anneal conditions and minimizing intersections with fracture planes to enhance mechanical robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the contact structure is annealed to reduce contact resistance, then the electrical performance is improved, but the mechanical strength decreases due to increased susceptibility to cracking and breaking
Solution Approach 1:
The contact structure is divided into multiple discrete annealed regions arranged in patterns rather than a continuous annealed area. This segmentation allows the structure to maintain low contact resistance in the annealed regions while unannealed regions provide mechanical strength and resistance to cracking.
Solution Approach 2:
Different regions of the contact structure have different properties: annealed regions provide low contact resistance for electrical performance, while unannealed regions maintain high mechanical strength. This local differentiation of properties resolves the contradiction between electrical and mechanical requirements.
2Power
If larger area semiconductor devices are used to improve device performance, then the power handling capability increases, but the likelihood of breaking and cracking increases due to handling stresses and thermomechanical stresses
Solution Approach 1:
The annealed contact regions are segmented into discrete patterns that avoid continuous lines parallel to fracture planes. This segmentation interrupts potential crack propagation paths while still providing sufficient annealed area for low contact resistance, allowing larger devices to maintain mechanical robustness.
Solution Approach 2:
The annealed regions are arranged in asymmetric patterns that are deliberately nonparallel to the crystallographic fracture planes of the substrate. This asymmetric arrangement minimizes intersections with fracture planes, reducing the likelihood of crack initiation and propagation under thermomechanical stress.
3Ease of manufacture
If annealed regions are formed parallel to fracture planes to simplify manufacturing, then the manufacturing process is easier, but the mechanical robustness decreases due to increased intersections with fracture planes
Solution Approach 1:
The annealed regions are deliberately oriented at angles nonparallel to the crystallographic fracture planes (such as 45 degrees or other optimized angles). This asymmetric orientation minimizes the number of intersections between annealed regions and fracture planes, reducing crack propagation risk while maintaining manufacturability through patterned annealing processes.
Solution Approach 2:
Instead of arranging annealed regions in simple linear patterns parallel to substrate edges, the invention uses two-dimensional patterned arrangements that account for the three-dimensional stress states and fracture plane orientations. This dimensional approach optimizes both mechanical robustness and electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the mechanical robustness of semiconductor devices by reducing the likelihood of cracking and breaking, while maintaining suitable contact resistance, thus enhancing their reliability and performance.
Implementation Method 1
Contact structures that include a metal layer and a substrate of a semiconductor device may be annealed to provide suitable contact resistance
Implementation Method 2
the plurality of annealed regions form a silicide of the metal layer
Data Source
AI summary
Contact structures for semiconductor devices are disclosed. Contact structures that include a metal layer and a substrate of a semiconductor device may be annealed to provide suitable contact resistance. Localized annealed regions may be formed in a pattern within the contact structure to provide a desired contact resistance while reducing exposure of other portions of the semiconductor device to anneal conditions. The annealed regions may be formed in patterns that reduce intersections between annealed regions and fracture planes of the substrate, thereby improving mechanical robustness of the semiconductor device. The patterns may include annealed regions formed in lines that are nonparallel with fracture planes of the substrate. The patterns may also include annealed regions formed in lines that are nonparallel with peripheral edges of the substrate.