Patterned Doped Layer for Semiconductor Contact Resistance
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Solution Overview
Problem
The conventional lower temperature poly silicon (LTPS) process for forming doped layers in thin film transistor devices is costly due to the high cost of implant apparatuses, making it challenging to achieve low resistance doped layers for large size substrates.
Innovation Solution
A semiconductor device and electroluminescent device are designed with contact electrodes and doped gate electrodes formed using a non-implant process, specifically through a patterned doped layer that includes a doped gate electrode and contact electrodes, where an annealing process reduces resistance, enabling efficient electrical performance without the need for expensive implant apparatuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ion implant process is used to form doped layer, then contact resistance is reduced, but manufacturing cost increases due to expensive implant apparatus
Solution Approach 1:
The patent extracts the doping function from the expensive ion implantation process and transfers it to a standard semiconductor fabrication process using a patterned doped layer formed by conventional lithography and deposition techniques. This separates the low-resistance contact formation from the costly implant apparatus while achieving the same electrical performance through alternative means.
Solution Approach 2:
The invention replaces the expensive, complex ion implantation system with a simpler, more economical patterned doped layer approach that uses standard fabrication equipment. The doped layer is formed as a discrete structural element that can be created using conventional, cost-effective processes rather than requiring specialized implantation infrastructure.
2Reliability
If ion implant apparatus is introduced for large size substrate process, then doped layer with low resistance can be formed, but device complexity and process difficulty increase
Solution Approach 1:
The patterned doped layer serves multiple functions simultaneously: it provides low-resistance contacts, defines gate electrode regions, and structures the semiconductor device architecture. This multi-functional approach eliminates the need for separate ion implantation steps and simplifies the overall manufacturing process while achieving the desired electrical characteristics.
Solution Approach 2:
The invention merges the doped layer formation with the gate electrode structure definition into a single patterned layer. By combining these functions into one integrated structure formed through conventional processes, the patent eliminates the need for complex ion implantation equipment and reduces process steps while maintaining low resistance performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces contact resistance, and enhances electrical performance, allowing for the application of these devices in large size display panels.
Implementation Method 1
an annealing process reduces resistance
Data Source
AI summary
A semiconductor device, disposed on a substrate, includes a first channel layer, a patterned doped layer, a gate insulating layer, a conducting gate electrode, a second channel layer, a first electrode and a second electrode, and a third electrode and a fourth electrode. The first channel layer is disposed on the substrate and in a first region. The patterned doped layer includes a doped gate electrode disposed in a second region, and two contact electrodes electrically connected to two sides of the first channel layer, respectively. The conducting gate electrode is disposed on the gate insulating layer in the first region. The second channel layer is disposed on the gate insulating layer in the second region. The first electrode and the second electrode are electrically connected to the contact electrodes, respectively. The third electrode and the fourth electrode are electrically connected to two sides of the second channel layer, respectively.