Patterned Seal Rings for IC Stress Protection and Interconnects
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Solution Overview
Problem
Existing semiconductor manufacturing techniques face challenges in protecting integrated circuits during the dicing process, as external stress can cause cracking without adequate seal ring protection, and existing seal ring structures are not versatile enough to accommodate various IC product configurations.
Innovation Solution
The implementation of a seal ring structure that surrounds integrated circuits on a semiconductor wafer, formed by patterning metal compounds using multiple circuit formation process steps, allowing for selective reuse of photomasks to create different IC product configurations, and includes inner and outer seal rings with optional openings for interconnecting circuit units across scribe lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If seal ring structures are formed to protect integrated circuits during dicing, then stress protection and reliability are improved, but device complexity and manufacturing process steps increase
Solution Approach 1:
The patent applies universality by designing a single seal ring structure that serves multiple functions: it provides stress protection during dicing, enables selective trace passage for inter-die connections, and accommodates different IC product configurations. The seal ring is formed using the same metal layers and via layers as the interconnect structure, making it a multi-functional element rather than a separate protective feature.
Solution Approach 2:
The patent merges the seal ring structure with the existing metal interconnect layers and via layers of the IC. Instead of creating a separate protective structure, the seal ring is formed by patterning the same metal compounds used for circuit interconnections, thereby combining protection and electrical functionality into a single integrated structure.
2Reliability
If complete seal rings are formed around all electronic circuits, then stress protection is improved, but manufacturing precision and photomask reuse flexibility deteriorate
Solution Approach 1:
The patent applies segmentation by forming different seal ring configurations for different regions of the semiconductor wafer. Inner seal rings are formed around individual electronic circuits, while outer seal rings are formed around groups of circuits. This segmentation allows selective passage of traces through inner seal rings while maintaining complete outer seal rings for stress protection, enabling photomask reuse across different IC product configurations.
Solution Approach 2:
The patent applies local quality by providing different seal ring structures in different regions of the wafer. Some regions have complete outer seal rings for maximum protection, while other regions have inner seal rings with openings to allow trace passage. This local differentiation enables both stress protection and inter-die connections without compromising manufacturing precision.
3Productivity
If outer seal rings are cut during dicing to separate dies, then die separation is achieved, but stress protection capability deteriorates
Solution Approach 1:
The patent applies dimensionality change by transitioning from complete outer seal rings on the wafer to partial outer seal rings on individual dies. The outer seal rings are formed completely around groups of electronic circuits on the wafer, but are cut during dicing to separate dies. This dimensional transition allows die separation while the remaining portions of the outer seal rings continue to provide stress protection on each die.
Data Source
AI summary
Aspects of the disclosure provide an integrated circuit (IC) formed on a die. The IC includes first one or more electronic circuits and a seal ring structure. The first one or more electronic circuits are disposed on a first semiconductor substrate. The first semiconductor substrate is diced from a semiconductor wafer. The seal ring structure is configured to surround the first one or more electronic circuits. The seal ring structure is formed by patterning one or more layers of metal compounds on the semiconductor wafer using two or more circuit formation process steps. The seal ring structure includes a remaining portion of a complete seal ring structure after a dicing process step that cuts the complete seal ring structure. The complete seal ring structure has been formed on the semiconductor wafer to surround the first one or more electronic circuits and at least second one or more electronic circuits on a second semiconductor substrate that is diced from the semiconductor wafer.