Patterned Substrate Design for Group III Nitride Epitaxy

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Solution Overview

Problem

Existing semiconductor technologies face challenges in minimizing dislocation density in semiconductor layers, particularly for deep ultraviolet light emitting diodes (DUV LEDs), which affects device efficiency, and current methods for stress reduction in patterned substrates have limitations in achieving dislocation-free growth.

Innovation Solution

A patterned substrate with a substantially flat top surface and stress-reducing regions, such as openings, is used to grow group III-nitride semiconductor layers with high aluminum concentration, where the root mean square roughness is less than 0.5 nanometers, and the openings have a characteristic size between 0.1 microns and five microns, allowing for effective stress relief and dislocation reduction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional substrate patterning techniques are used to reduce dislocation density, then device efficiency improves, but manufacturing complexity increases

Engineering Contradiction:
Improvedislocation densityVSAvoidsubstrate patterning complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The substrate surface is segmented into discrete patterned regions (protrusions or depressions) separated by spacing, creating isolated growth zones that prevent dislocation propagation while maintaining manageable manufacturing complexity through regular geometric patterns

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the substrate are given different local properties - patterned regions with specific geometries (convex protrusions or concave depressions) that locally control dislocation behavior, while non-patterned regions maintain standard characteristics, allowing targeted stress management without global complexity

Inventive Principle:
Principle #3Local quality

2Reliability

If stress-reducing patterned structures are introduced in the substrate, then semiconductor layer quality improves, but manufacturing precision requirements increase

Engineering Contradiction:
Improvesemiconductor layer qualityVSAvoidpatterned structure precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patterned structures utilize curved geometries (convex or concave surfaces) that naturally distribute stress more uniformly compared to sharp angular features, reducing sensitivity to manufacturing tolerances while maintaining effective stress reduction and improving layer quality

Inventive Principle:
Principle #14Spheroidality (Curvature)

Solution Approach 2:

The invention provides specific parameter ranges for pattern dimensions (size, depth, spacing) that optimize both stress reduction effectiveness and manufacturing feasibility, allowing relaxation of precision requirements while maintaining layer quality through carefully selected geometric parameters

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The approach results in a significant reduction of dislocation density and stress in the semiconductor layers, leading to improved efficiency and performance of light emitting devices by promoting dislocation-free growth and stress relief through the use of patterned substrates with specific surface features.

Implementation Method 1

A patterned substrate with a substantially flat top surface and stress-reducing regions, such as openings, is used to grow group III-nitride semiconductor layers with high aluminum concentration

Methodology Applied
Scientific EffectStress relaxation: Stress Relaxation

Implementation Method 2

The approach results in a significant reduction of dislocation density and stress in the semiconductor layers, leading to improved efficiency and performance of light emitting devices by promoting dislocation-free growth

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS10050175B2Patterned layer design for group III nitride layer growth
Publication Date: 2018.08.14 SENSOR ELECTRONIC TECHNOLOGY INC
  • US10050175B2 patent drawing
  • US10050175B2 patent drawing
  • US10050175B2 patent drawing

AI summary

A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.