PCB Connection Testing via Capacitive Coupling
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Solution Overview
Problem
Current methods for detecting open and shorted connections on printed circuit boards (PCBs) using test pads disrupt high-speed signals and are limited by the need for specific frequency ranges, leading to unreliable signal transmission and reduced fault coverage.
Innovation Solution
A vectorless testing method utilizing a virtual signal generator to produce test signals on PCBs, which are capacitively coupled to a detector plate for time domain analysis, allowing for the identification of open and shorted connections without the need for test pads and independent of scan chain length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If test pads are connected to signal paths for testing, then electrical access for testing is improved, but impedance changes cause signal transmission reliability to deteriorate
Solution Approach 1:
The patent introduces an intermediary coupling mechanism (capacitive coupling through detector plate) between the test equipment and the signal path. This allows testing without direct electrical connection, thus avoiding impedance changes while still enabling signal detection for fault identification
Solution Approach 2:
The patent extracts the testing function from the signal path by using boundary scan devices within ICs to generate test signals internally. This eliminates the need for external test pads and their associated impedance disruptions, allowing testing to occur without modifying the signal path
2Reliability
If periodic test signals are applied at low frequencies for opens measurement, then fault coverage is improved, but signal amplitude detected decreases
Solution Approach 1:
The patent uses periodic square wave test signals generated by boundary scan devices to stimulate the circuit under test. The periodic nature allows for consistent fault detection while the signal characteristics are optimized for capacitive coupling detection, improving both fault coverage and measurement precision
Solution Approach 2:
The patent implements feedback by comparing the detected coupled signal against expected characteristics. This allows the system to distinguish between genuine fault conditions and normal signal variations, improving measurement precision while maintaining comprehensive fault coverage
3Measurement precision
If test frequency is increased above 10 KHz for better signal amplitude, then measurement precision is improved, but false passes increase due to coupling into detector plate
Solution Approach 1:
The patent dynamically adjusts the test approach by using time-domain analysis of the coupled signal characteristics. This allows the system to adapt to different frequency conditions and distinguish between genuine faults and false positives, maintaining measurement precision while reducing false pass rates
Solution Approach 2:
The patent replaces traditional frequency-domain measurement approaches with time-domain analysis. This substitution allows for more accurate fault detection by analyzing the temporal characteristics of coupled signals, reducing false passes while maintaining high measurement precision
4Adaptability or versatility
If boundary scan chain length varies across different board types, then adaptability is improved, but stimulus frequency control becomes difficult
Solution Approach 1:
The patent makes the boundary scan device serve multiple functions: generating test signals, controlling stimulus frequency, and detecting faults. This universal approach allows consistent frequency control across different board types and scan chain lengths, maintaining both adaptability and ease of operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable detection of connection faults on high-speed signals, reducing false reports and improving fault coverage by analyzing transient characteristics of the coupled signals, thereby overcoming the limitations of existing methods.
Implementation Method 1
which are capacitively coupled to a detector plate for time domain analysis
Data Source
AI summary
A test system and method for identifying open and shorted connections on a printed circuit board (PCB). An integrated circuit (IC) unit on the PCB is configured to generate a test signal on an output pin connected to a test pin on a second device, connector, or socket on the PCB. For a connection, the test signal is capacitively coupled to a detector plate proximal the second device. Based on the signal coupled to the detector, time domain analysis is performed on the coupled signal to determine if the test pin has a good connection to the PCB or if the pin is open or shorted. Analysis may include cross-correlating the coupled signal with a learned signal obtained from a known “good” PCB. The test pin may pass the test if the cross-correlation is within a specified threshold window. If the test fails, additional tests may be performed to troubleshoot the cause of the testing failure.