PCB Convex Polygon Layout for GaN Transistor Current Sharing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In power electronic modules, ensuring uniform current distribution among transistors in parallel configurations is challenging, leading to increased switching losses and reduced reliability, particularly for fast-switching transistors like Gallium Nitride (GaN) and Silicon Carbide Metal-Oxide-Semiconductor (SiCMOS) due to unequal parasitic elements and unpredictable external connectivity.
Innovation Solution
A printed circuit board design featuring N power switching cells arranged in a convex polygon configuration with decoupling capacitors and gate driver circuits, where each transistor leg consists of two transistors in series, and the DC lines are positioned to encircle the cells to create a laminated DC bus, ensuring uniform current sharing and minimizing parasitic leakage inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple power transistors are used in parallel to increase current capacity, then the electrical current capacity is improved, but the uniformity of current distribution deteriorates due to unequal parasitic elements and external connectivity
Solution Approach 1:
The patent applies asymmetry by deliberately designing the PCB layout with non-uniform trace routing and component placement to compensate for inherent parasitic element variations. The external connectivity is intentionally made asymmetric to balance the overall current distribution, counteracting the asymmetric parasitic elements within each transistor package.
Solution Approach 2:
The patent implements equipotentiality through carefully designed low-inductance power and ground planes, ensuring that all transistor connections experience equal potential during switching. The PCB layout minimizes voltage drops and maintains equipotential surfaces across all parallel transistor connections, eliminating current distribution imbalances caused by potential differences.
2Speed
If fast switching transistors (GaN, SiCMOS) are used to improve switching speed, then the switching performance is improved, but the current sharing uniformity deteriorates due to unequal parasitic leakage inductance
Solution Approach 1:
The patent applies local quality by optimizing the immediate vicinity of each fast-switching transistor with localized decoupling capacitors, ground vias, and trace routing. Each transistor's local environment is carefully tuned to compensate for its specific parasitic characteristics, ensuring uniform current sharing despite variations in switching speed and parasitic leakage inductance.
Solution Approach 2:
The patent uses copying by creating identical, replicated PCB patterns for each parallel transistor connection. The same footprint, trace geometry, and component placement are copied for each transistor, ensuring that all transistors experience identical electromagnetic environments and parasitic elements, thereby achieving uniform current distribution.
3Object-affected harmful factors
If transistors are placed close together to reduce parasitic inductance, then the parasitic leakage inductance is reduced, but the electromagnetic interference between transistors increases
Solution Approach 1:
The patent applies the nested doll principle by placing decoupling capacitors inside the perimeter formed by each transistor's power and ground connections. This nested arrangement minimizes the loop area for high-frequency currents, reducing parasitic inductance while containing electromagnetic fields within localized regions, thereby preventing interference with adjacent transistors.
Solution Approach 2:
The patent uses intermediary elements such as ground vias, shielding traces, and decoupling capacitors positioned between adjacent transistors. These intermediaries act as electromagnetic barriers and current return paths, reducing parasitic inductance while preventing electromagnetic coupling and interference between neighboring transistor circuits.
Data Source
AI summary
A printed circuit board comprises N power switching cells operating in parallel and respectively comprising a transistor leg, at least one decoupling capacitor and a gate driver circuit. Each transistor leg comprises respective first and second transistors in series, a drain of the first transistor being connected to a positive DC line, a source of the second transistor being connected to a negative DC line, a source of the first transistor being connected to a drain of the second through a connection middle-point connected to an output terminal. Each gate driver circuit controls respective switching ON and OFF of the corresponding first and second transistors. The N transistor legs of the corresponding N power switching cells are positioned to substantially form a convex polygon having N edges of substantially the same length, each one of the N transistor legs being positioned along one of the edges of the convex polygon.