High-Density PCB Core Layer via Stacking Fabrication
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Solution Overview
Problem
Conventional flip-chip and chip scale packaging technologies face limitations in achieving line widths and line spacings below 40 μm, hindering the reduction of overall board density in electronic products with increasing I/Os and smaller IC features.
Innovation Solution
A method involving multiple-layer blind via stacking on a core layer using plating through hole filling, encapsulation, grinding, and advanced etching techniques, followed by copper coating and pattern plating to create high-density blind via structures, enabling line widths and spacings of 20/20 μm through the use of SAP technology for enhanced design flexibility and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional flip-chip and chip scale packaging technologies are used, then packaging is achieved, but line width and line spacing cannot reach 40 μm or below
Solution Approach 1:
The patent divides the via structure into multiple segments: PTH (plating through hole) and multiple layers of blind vias stacked on the PTH. This segmentation allows each via type to be fabricated using optimized processes, enabling line widths and spacings below 40 μm while maintaining manufacturability through standardized fabrication steps for each segment type
Solution Approach 2:
The patent transitions from traditional planar via structures to three-dimensional stacked blind via structures on PTH. By adding the vertical stacking dimension, the design achieves higher density and finer line dimensions (20/20 μm capability) while distributing the complexity across multiple fabrication layers rather than requiring extreme precision in a single plane
2Manufacturing precision
If blind via stacking is increased to improve board density, then manufacturing complexity increases
Solution Approach 1:
The PTH (plating through hole) is fabricated first as a preliminary structure before stacking blind vias on top. This preliminary action establishes a stable foundation that simplifies subsequent blind via fabrication, as each blind via can be independently formed on the pre-existing PTH structure without requiring complex simultaneous multi-layer alignment
Solution Approach 2:
Multiple blind vias are nested stacked on the PTH structure, with each blind via containing copper filling and insulation material within defined boundaries. This nesting approach allows multiple via structures to be integrated in a compact vertical arrangement, achieving high board density while organizing the fabrication process into manageable sequential steps for each nested layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves the design flexibility and electrical reliability of circuits, allowing for increased blind via stacking and achieving the capability for 20/20 μm line width/spacing, thereby enhancing the overall board density and mechanical strength.
Implementation Method 1
a thin copper metal layer is coated on the surface at a thickness of 3 ̃12 μm
Implementation Method 2
by using laser etching, sand blasting, plasma etching, chemical etching, and other methods for partially removing the filling material
Implementation Method 3
the image transfer and pattern plating operations are performed to fill and to level the depression portion of the filling material up to desired thickness, and to produce the copper pad, and the necessary circuitry
Data Source
AI summary
Structure and method of making a board having plating though hole (PTH) core layer substrate and stacked multiple layers of blind vias. More stacking layers of blind vias than conventional methods can be achieved. The fabrication method of the board having high-density core layer includes the following: after the making of the PTH, the filling material filled inside the PTH of the core layer is partially removed until the PTH has reached an appropriate flattened depression using etching; then image transfer and pattern plating are performed to fill and to level the depression portion up to a desired thickness to form a copper pad (overplating) as the core layer substrate is forming a circuit layer; finally using electroless copper deposition and the pattern plating to make the product.