PCB DC Layer Symmetry for Parasitic Vibration Compensation
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Solution Overview
Problem
Existing printed circuit boards for converting input phases to output phases struggle to effectively compensate for parasitic vibrations and interference emissions generated by switching procedures, particularly in DC motor applications, leading to overshooting issues.
Innovation Solution
A printed circuit board design featuring conductive DC+ and DC− layers covering at least 75% of the input phase surface area, with identical layouts and configurations to ensure symmetrical stray values, along with strategically placed power semiconductors and intermediate circuit capacitors, effectively compensates for parasitic vibrations and interference emissions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional printed circuit board designs are used with standard layer coverage, then manufacturing costs are reduced and manufacturing precision is maintained, but parasitic vibrations and interference emissions from switching procedures cannot be effectively compensated
Solution Approach 1:
The input phase surface area is segmented into distinct functional zones: a cover surface area (at least 75% coverage) dedicated to DC+ and DC− layers for compensation, and remaining areas for other circuit functions. This segmentation allows the compensation function to be isolated and optimized without complicating the entire board design.
Solution Approach 2:
The DC+ layer and DC− layer are merged into a symmetrical configuration within the cover surface area, where both layers have identical layouts and overlap geometrically. This merging creates symmetrical stray values that compensate for parasitic effects generated by power semiconductor switching.
2Object-affected harmful factors
If DC+ and DC− layers are configured with identical layouts in the cover surface area, then parasitic vibrations are compensated through symmetrical stray values, but manufacturing precision requirements increase
Solution Approach 1:
The DC+ layer and DC− layer are configured to have equipotential symmetry in terms of their geometric layout and conductor path arrangements. This symmetrical configuration ensures that stray capacitances and leakage inductances are substantially equal, creating a balanced electromagnetic environment that compensates for parasitic vibrations without requiring ultra-precise manufacturing tolerances.
3Object-affected harmful factors
If the cover surface area is increased to at least 75% of the input phase surface area, then compensation effectiveness is improved, but the area available for other circuit components is reduced
Solution Approach 1:
The compensation function is localized to the cover surface area where DC+ and DC− layers are configured with identical layouts. This local quality approach concentrates the compensation effect in a specific region (at least 75% of input phase surface area) while allowing other regions of the circuit board to be optimized for different functions, thus balancing compensation effectiveness with overall circuit layout flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces parasitic vibrations and interference emissions, allowing for the use of more delicate components, reducing the need for extensive filtering, and enabling more economic production while maintaining effective operation across a wide voltage range.
Implementation Method 1
The corresponding configuration results in stray values in these layers, e.g. stray capacitances and leakage inductances, that are substantially equal
Implementation Method 2
at least one conductive DC+ layer for conducting a DC+ potential of the input phase and one conductive DC− layer for each DC+ layer for conducting a DC− potential of the input phase
Data Source
AI summary
A printed circuit board (1) for converting an input phase to at least one output phase (U,V,W), which has an input phase surface area with at least one conductive DC+ layer (28) and one conductive DC− layer (29) for each conductive DC+ layer (28), for conducting the input phase. There is at least one high-side power semiconductor (6) for each output phase (U, V, W) and one low-side power semiconductor (7) for each high-side power semiconductor (6), for switching the input phase. The at least one DC+ layer (28) corresponding to a respective DC− layer (29) is formed in a cover surface area (2), which covers at least 75% of the input phase surface area.