Printed Circuit Board With Dummy Lanes For Wiring Defect Bypass
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Solution Overview
Problem
Existing printed circuit boards face challenges in maintaining normal function and reliability when defects such as open or shorted wirings occur, particularly during the implementation of fine wiring, which can lead to reduced yield and operational failures.
Innovation Solution
The printed circuit board design incorporates a first and second integrated circuit chip with demultiplexer and multiplexer circuits, respectively, along with multiple wirings that include dummy lanes. This configuration allows for signal transmission by bypassing defective wirings to dummy lanes through lane shifting, ensuring continuous operation even with defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine wiring is implemented to achieve high-density circuits, then circuit density and integration capability are improved, but manufacturing yield and reliability deteriorate due to increased susceptibility to wiring defects
Solution Approach 1:
The patent applies preliminary action by pre-configuring dummy lanes alongside functional lanes during the circuit design phase. These dummy lanes are prepared in advance as backup pathways, so that when wiring defects occur in fine circuits, the system can immediately switch to pre-prepared alternative routes without requiring post-manufacturing modifications or rework.
Solution Approach 2:
The patent implements beforehand cushioning by introducing redundant dummy wiring lanes that act as a buffer against wiring defects. These extra lanes provide a safety margin, allowing the system to tolerate open or shorted wirings in fine circuits while maintaining operational functionality through lane shifting to the dummy lanes.
2Reliability
If wiring defects such as open or shorted wirings occur, then operational functionality deteriorates, but with dummy lanes and lane shifting, normal function can be maintained
Solution Approach 1:
The patent uses dummy lanes as intermediary elements that mediate between functional lanes and the system output. When wiring defects occur in functional lanes, the dummy lanes serve as intermediate pathways that can receive and transmit signals, effectively bridging the gap caused by defective wirings and maintaining system functionality.
Solution Approach 2:
The patent applies dynamics by implementing lane shifting capability that allows the system to dynamically reconfigure signal pathways based on detected wiring defects. The system can adaptively switch from defective functional lanes to healthy dummy lanes, transforming a static wiring configuration into a dynamic, defect-tolerant system.
3Quantity of substance
If multiple wirings are used for signal transmission, then signal capacity is improved, but the probability of defects increases
Solution Approach 1:
The patent applies segmentation by dividing the signal transmission capacity into multiple independent lanes, including both functional lanes and dummy lanes. This segmentation allows individual lanes to be independently evaluated for defects, and defective lanes can be isolated and bypassed while other lanes continue to operate, thereby maintaining overall signal capacity despite the presence of multiple wirings.
Data Source
AI summary
A printed circuit board includes a first wiring portion including a plurality of first wirings, a first integrated circuit chip connected to one side of the first wiring portion, the first integrated circuit chip configured to convert N signals into one signal, where N is a natural number, a second integrated circuit chip connected to an opposite side of the first wiring portion, the second integrated circuit chip configured to convert one signal into N signals, a second-first wiring portion connected to the first integrated circuit chip, the second-first wiring portion including a plurality of second-first wirings, and a second-second wiring portion connected to the second integrated circuit chip, the second-second wiring portion including a plurality of second-second wirings. X and Y1 satisfy Y1/N<X, in which X is the number of the plurality of first wirings and Y1 is the number of the plurality of second-first wirings.


