PCB Edge Heat Dissipation for Thick 3D Storage Packages
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Solution Overview
Problem
3D semiconductor storage devices face challenges in heat dissipation due to their increased thickness, which prevents the inclusion of thermal interface material (TIM) on the top surface within standard enclosures, limiting their ability to efficiently manage heat generated during operation.
Innovation Solution
The implementation of thermally conductive edge layers on a printed circuit board (PCB) that are exposed during depaneling, allowing for the mounting of TIMs on the side edges of the PCB, creating a thermal conduction pathway through the PCB edges and out of the enclosure, thereby omitting the need for a TIM on the top surface of the package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D NAND technology is used to increase storage capacity, then storage capacity is improved, but package thickness increases which prevents inclusion of TIM on top surface
Solution Approach 1:
The patent transitions thermal management from the vertical dimension (top surface TIM) to the horizontal dimension (edge layers). By exposing thermally conductive layers at the PCB edges and placing TIMs horizontally along the enclosure sides, heat dissipation occurs laterally rather than vertically, resolving the space conflict caused by increased package thickness.
2Temperature
If package thickness is reduced to accommodate TIM on top surface, then heat dissipation is improved, but storage capacity is reduced due to fewer stacked layers
Solution Approach 1:
The invention redirects the thermal management function from the vertical axis to the horizontal axis. Instead of reducing package thickness to fit TIM on the top surface, the solution uses edge layers and side-mounted TIMs to conduct heat laterally, allowing full utilization of vertical stacking for storage capacity while maintaining effective heat dissipation through a different spatial pathway.
3Temperature
If TIM is mounted on top surface of package, then heat dissipation is improved, but standard form factor of enclosure is compromised
Solution Approach 1:
The patent extracts the TIM from its conventional position on the top surface of the semiconductor package and relocates it to the horizontal edges of the enclosure. This extraction allows the top surface to remain flat and within standard form factor specifications while heat dissipation function is preserved through the relocated edge-mounted TIMs.
Solution Approach 2:
By moving TIM placement from the vertical top surface to the horizontal edge regions, the invention maintains the standard vertical profile of the enclosure while establishing a new horizontal thermal conduction pathway that does not interfere with the approved form factor dimensions.
4Temperature
If edge layers are exposed during depaneling for thermal conduction, then heat dissipation is improved, but manufacturing complexity increases
Solution Approach 1:
The thermally conductive layers are pre-configured within the PCB structure during panel fabrication, positioned to be exposed at the edges. This preliminary preparation ensures that when depaneling occurs, the thermal conduction pathway is already in place, requiring only simple attachment of TIMs to the exposed edges without complex additional manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively dissipates heat from 3D semiconductor packages by utilizing the PCB's edge thermally conductive layers and TIMs, ensuring efficient heat management without compromising the standard form factor of the enclosure.
Implementation Method 1
one or more thermally conductive layers extending to an edge of the heat conduction medium; a thermal interface material (TIM) mounted adjacent to the edge of the heat conduction medium; wherein a thermal conduction path exists to conduct heat away from the semiconductor package through the edge of the PCB
Data Source
AI summary
A semiconductor storage device includes semiconductor packages mounted on a printed circuit board (PCB) and encased within an enclosure. The semiconductor storage device includes thermal interface material mounted on side edges of the PCB. During depaneling (separation) of individual semiconductor storage devices from a PCB panel, edges of the PCB may be overcut to expose thermally conductive edge layers provided within the interior the PCB. The thermal interface material may be positioned adjacent to the exposed thermally conductive edge layers to conduct heat away from a semiconductor package through the side edges of the PCB and out of sides of the enclosure.