Multi-layered PCB ESD Protection via Electro-static Releasing Layer
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Solution Overview
Problem
Integrated circuits (ICs) and printed circuit boards (PCBs) are vulnerable to electrostatic discharge (ESD) damage during fabrication and assembly, with existing ESD protection methods like TVS or Zener diodes complicating circuit design and increasing costs, and not compatible with miniaturization trends.
Innovation Solution
A multi-layered circuit board design incorporating a patterned conductive layer, an electro-static releasing layer, and a solder mask layer with strategically placed notches and through holes to facilitate point discharge and prevent ESD damage without expanding the circuit layout area or increasing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TVS or Zener diodes are used for ESD protection, then ESD protection capability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the ESD protection function from traditional discrete components (TVS/Zener diodes) and integrates it directly into the PCB structure through a dedicated electro-static releasing layer with through-holes, eliminating the need for separate protection components while maintaining protection capability
Solution Approach 2:
The PCB structure itself provides ESD protection through its own design features (electro-static releasing layer, through-holes, conductive patterns) rather than requiring external protection components, making the protection mechanism self-contained and eliminating additional device complexity
2Reliability
If TVS or Zener diodes are used for ESD protection, then ESD protection capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent removes the need for expensive discrete ESD protection components by extracting the protection function and embedding it into the PCB manufacturing process itself through specialized layer structures that can be produced using standard PCB fabrication techniques
Solution Approach 2:
The ESD protection structure is merged with the PCB's existing multi-layer structure, combining the electro-static releasing layer with through-holes and conductive patterns that are already part of the PCB fabrication process, thereby avoiding additional manufacturing steps and costs
3Reliability
If traditional ESD protection components are used, then ESD protection is achieved, but circuit layout area increases
Solution Approach 1:
The patent transitions from planar ESD protection components to a vertical three-dimensional structure using through-holes that penetrate multiple PCB layers, utilizing the Z-dimension to provide protection without consuming additional planar layout space
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces ESD damage to ICs and PCBs by allowing efficient electrostatic charge release without additional components, maintaining a compact circuit layout and cost-effectiveness.
Implementation Method 1
the electro-static charges are often released through point discharge (or marginal discharges)
Implementation Method 2
the electro-static charges are often released through point discharge (or marginal discharges). When the surface radius of curvature of an object is large (e.g., at a tip), the electric field increases drastically such that air around the object is ionized and converted into positive and negative ions. Discharge then occurs at the tip which attracts and neutralizes counter ions
Data Source
AI summary
An electro-static discharge (ESD) protection structure includes a first insulation layer (having a first surface, a second surface opposite to the first surface, and a through hole), a patterned conductive layer (located on the first surface), an electro-static releasing layer (located on the second surface), and a solder mask layer. At least one portion of the patterned conductive layer surrounds the through hole. The electro-static releasing layer is electrically insulated from the patterned conductive layer. At least one portion of the electro-static releasing layer is around the through hole. The solder mask layer covers the first insulation layer and a portion of the patterned conductive layer and exposes a portion of the patterned conductive layer surrounding the through hole. A multi-layered circuit board including a second insulation layer, a power supply layer, a third insulation layer and the ESD protection structure is also provided.