Printed Wiring Board Foil Roughness for Stress and Adhesion
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Solution Overview
Problem
Existing printed wiring boards face challenges in maintaining connection reliability and preventing peeling of through-hole conductors due to residual stress and unevenness in the mat surfaces of metal foils, which can lead to defects and reduced performance.
Innovation Solution
The printed wiring board design features a core substrate with through-hole conductors and lands, alternating resin insulating layers, and via conductors, where the mat surfaces of metal foils have controlled roughness to reduce stress and enhance adhesion, with specific roughness ratios and thicknesses of metal foils and electrolytic plating films to improve connection reliability and prevent peeling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the mat surface roughness of metal foils is increased to enhance adhesion, then connection reliability improves, but residual stress increases causing peeling defects
Solution Approach 1:
The patent applies different surface roughness characteristics to different locations: the mat surfaces of metal foils have larger roughness (Rz1-Rz4) to enhance adhesion to insulating layers, while the inner surfaces of through-hole conductors have smaller roughness (Rz11-Rz14) to reduce stress concentration and prevent peeling. This local differentiation resolves the contradiction between adhesion enhancement and stress reduction.
Solution Approach 2:
The patent controls specific roughness parameters (Rz values) of metal foil mat surfaces within defined ranges (3.0μm≤Rz≤6.0μm for outer layers, 1.5μm≤Rz≤3.0μm for inner layers) to optimize both adhesion strength and stress distribution. By precisely adjusting these surface roughness parameters, the patent achieves reliable connections while minimizing residual stress-induced peeling.
2Ease of manufacture
If uniform roughness is applied to all metal foil surfaces to simplify manufacturing, then manufacturing complexity decreases, but connection reliability and stress distribution are compromised
Solution Approach 1:
The patent implements differentiated roughness control for various metal foil surfaces: outer conductor layers have larger roughness (Rz1-Rz4: 3.0-6.0μm) for strong adhesion, while inner through-hole conductor surfaces have smaller roughness (Rz11-Rz14: 1.5-3.0μm) for stress reduction. This local quality differentiation optimizes both manufacturing feasibility and connection reliability.
Solution Approach 2:
The patent segments the metal foil surfaces into different functional zones with distinct roughness characteristics. By dividing the surfaces into outer layers (requiring high adhesion) and inner through-hole surfaces (requiring stress management), the patent achieves reliable connections while maintaining manufacturing practicality through targeted roughness control in each segment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces residual stress, enhances adhesion, and increases connection reliability between conductor layers and the core substrate, preventing peeling and defects, thereby improving the overall performance and reliability of the printed wiring board.
Implementation Method 1
Each of the first through-hole lands, second through-hole lands, first via lands, second via lands, outermost first conductor layer and outermost second conductor layer includes a metal foil, a seed layer formed on the metal foil, and an electrolytic plating film formed on the seed layer
Data Source
AI summary
A printed wiring board includes a core substrate and first and second build-up layers. The substrate includes a core layer, through-hole conductors formed in through holes such that each through hole has first opening tapering from first toward second surface of the core layer, and second opening tapering from second toward first surface of the core layer, and first and second through-hole lands directly connected to the through-hole conductors. Each build-up layer includes an insulating layer, via conductors, via lands, an outermost insulating layer, an outermost conductor layer, and outermost via conductors. Each of the through-hole lands, via lands and outermost conductor layers includes a metal foil, a seed layer and an electrolytic plating film. The foils have mat surfaces such that the mat surfaces of the via lands has ten-point average roughness smaller than ten-point average roughness of the mat surfaces of the through-hole lands and outermost conductor layers.