Metallic Network Via Interconnection for PCB Thermal Resistance
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Solution Overview
Problem
Existing methods for manufacturing vias in multi-layered PCB stacks face thermal limitations due to the discrete nature of via interconnections, which restricts heat conduction and increases thermal resistance.
Innovation Solution
A method involving the partial dissolution of first dielectric layers with low glass transition temperature between vias, followed by metal filling of the vias and spaces between second dielectric layers with high glass transition temperature, creating a metallic network that enhances thermal conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If laser drilling is used to create small via diameter and high via density, then via interconnection capability is improved, but thermal resistance increases due to discrete interconnection limitation
Solution Approach 1:
The patent merges discrete via interconnections into a continuous metallic network by dissolving dielectric material between adjacent vias and filling the resulting spaces with conductive metal. This combines multiple discrete thermal paths into a unified continuous thermal conduction network, eliminating thermal resistance at dielectric interfaces and providing reliable thermal management for high-density via patterns.
2Temperature
If via size and via density are increased to improve thermal performance, then heat transfer capability is improved, but manufacturing complexity increases due to multiple successive steps
Solution Approach 1:
The patent performs preliminary dissolution of the dielectric material between vias before the metal filling step. By removing the dielectric barrier in advance, the subsequent metal deposition process can continuously fill both the via holes and the inter-via spaces in a single operation, creating the metallic network without requiring multiple separate drilling, filling, and etching cycles.
3Reliability
If metal density in PCB is increased to improve thermal conduction, then thermal resistance decreases, but production time and production costs increase
Solution Approach 1:
The patent changes the physical and chemical parameters of the dielectric material by selecting materials with specific glass transition temperatures (Tg). The first dielectric layer uses a material with low Tg (40-100°C) that dissolves readily in permanganate solution, while the second dielectric layer uses a material with high Tg (>100°C) that remains stable. This parameter differentiation enables selective dissolution and efficient metallic network formation in a streamlined process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases metal density between conductive layers, improves heat extraction from the PCB stack, and reduces intrinsic thermal resistance of via interconnections, leading to better thermal performance.
Implementation Method 1
a permanganate desmear process is performed on the multi-layered dielectric PCB stack to at least partially dissolve the first dielectric layers between the vias
Implementation Method 2
an electroless metallic deposition is performed on the multi-layered dielectric PCB stack, thus depositing a first metallic layer on internal walls of the plurality of vias, said first metallic layer also filling the spaces between the second dielectric layers
Implementation Method 3
a metallic electroplating filling is performed on the multi-layered dielectric PCB stack, thus filling the plurality of vias with a second metallic layer
Implementation Method 4
the heat follows the conductive paths due to better thermal conductivity than in the dielectric layer
Data Source
Figure 1a~1c
Figure 2a~2c
Figure 3~4
AI summary
A method for manufacturing vias in a multi-layered dielectric PCB stack (50) comprising a plurality of alternating first dielectric layers (52) and second dielectric layers (54), the first dielectric layers (52) comprising a first dielectric material with low glass transition temperature (Tg) and the second dielectric layers (54) comprising a second dielectric material with high glass transition temperature (Tg), a plurality of vias (64) being formed (202, 204) into said plurality of first dielectric layers (52) and second dielectric layers (54), the method comprising: - at least partially dissolving (206) the first dielectric layers (52) between the vias (64); - filling (208, 210) with metal (68, 70) the vias (64) and the spaces between the second dielectric layers (54) left void by the at least partial dissolution of the first dielectric layers (52), thus obtaining a metallic network (72) interconnecting the vias (64) each other.