PCB Semiconductor Package Layout for Warpage Reduction
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Solution Overview
Problem
The warpage phenomenon occurs in semiconductor packages due to thermal expansion coefficient differences between the PCB substrate and encapsulator, exacerbated by the miniaturization of the packages.
Innovation Solution
A method involving the formation of solder resist or insulating patterns on the PCB substrate, with specific dimensions and placements relative to semiconductor chips, followed by a mold layer application and cutting to form semiconductor packages, which reduces the mold layer volume and minimizes warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the thickness of the semiconductor package is reduced to achieve miniaturization, then the size of the semiconductor package is reduced, but the warpage phenomenon occurs more easily due to thermal expansion coefficient differences between PCB substrate and encapsulator
Solution Approach 1:
The patent divides the encapsulator into multiple segments by forming through-holes penetrating the encapsulator body. These through-holes create segmented regions that can independently accommodate thermal expansion differences, reducing overall warpage while maintaining package miniaturization
Solution Approach 2:
The patent introduces through-holes at specific locations within the encapsulator to locally address thermal expansion issues. The through-holes are strategically positioned to relieve stress in critical areas without compromising the overall structural integrity or increasing package size
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents warpage by controlling the mold layer volume through strategic pattern formation, ensuring structural integrity and reliability of miniaturized semiconductor packages.
Implementation Method 1
partially removing the solder resist layer through an exposure process and a development process, thereby forming solder resist patterns
Data Source
AI summary
A semiconductor package manufacturing method of the disclosure includes providing a PCB substrate that extends in a first direction and a second direction perpendicular to the first direction, forming a solder resist layer on the PCB substrate, partially removing the solder resist layer, thereby forming solder resist patterns, disposing semiconductor chips at opposite sides of each of the solder resist patterns, forming a mold layer covering a portion of the PCB substrate, covering the semiconductor chips, and covering at least a portion of each of the solder resist patterns, and cutting the PCB substrate and the mold layer, thereby forming semiconductor packages. In a third direction perpendicular to the first and second directions a height of the solder resist patterns may be greater than a height of the semiconductor chips while being smaller than a height of the mold layer.