Embedded PCB Pad Flatness for Fine Pitch Wire Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing embedded trace substrate method for manufacturing printed circuit boards results in non-flat wire bonding pads due to embedded insulating layers, which affects the bondability of chip connections and limits the number of wire bonding pads per unit area, especially in thin electronic products with fine pitch connections.
Innovation Solution
A printed circuit board design featuring external connection pads embedded in a single insulating layer with a flat surface, where the pads have the same thickness as the layer, and a separate insulating layer with a wiring pattern connected to the pads, allowing for fine pitch intervals and increased pad density without additional wiring patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the embedded trace substrate (ETS) method is used to manufacture a thin printed circuit board with fine pitch connection pads, then the pitch of connection pads can be reduced, but the wire bonding pad surface becomes non-flat due to embedded insulating layers, degrading bondability
Solution Approach 1:
The patent divides the connection pad structure into two separate functional layers: the first insulating layer contains only the external connection pads with flat exposed surfaces for wire bonding, while the second insulating layer contains the wiring patterns for electrical connections. This segmentation allows each layer to optimize its function independently, resolving the contradiction between fine pitch and flat surface requirement
Solution Approach 2:
The patent transitions from a single-layer embedded pad structure to a multi-layer configuration where pads and wiring patterns are separated in the vertical dimension. The external connection pads are positioned in the first insulating layer with flat top surfaces, while wiring patterns are placed in the second insulating layer, creating a three-dimensional arrangement that simultaneously achieves fine pitch and flat bonding surfaces
2Quantity of substance
If the pitch of wire bonding pads is minimized to increase the number of pads per unit area, then pad density increases, but the non-flat surface of embedded pads in ETS method reduces wire bonding reliability
Solution Approach 1:
By segmenting the pad and wiring functions into separate layers, the patent enables minimization of pad pitch in the first insulating layer without compromising surface flatness. The external connection pads can be densely packed while maintaining flat exposed surfaces, thereby increasing pad density without sacrificing wire bonding reliability
Solution Approach 2:
The second insulating layer acts as an intermediary that carries the wiring patterns away from the external connection pads. This allows the pads in the first layer to be positioned at minimal pitch for high density, while the wiring patterns in the second layer provide the necessary electrical connections without interfering with the flat pad surfaces
3Manufacturing precision
If external connection pads are embedded in a single insulating layer without other wiring patterns, then the pad surface remains flat and fine pitch is achieved, but additional insulating layers are required for wiring patterns
Solution Approach 1:
The patent utilizes the vertical dimension by stacking two insulating layers, with the first layer dedicated to external connection pads requiring flat surfaces, and the second layer containing wiring patterns. This three-dimensional arrangement maintains pad flatness and enables fine pitch while accommodating all necessary wiring functions through the layered structure
Data Source
AI summary
A printed circuit board includes a first insulating layer; an external connection pad embedded in a first surface of the first insulating layer and having a first externally exposed surface disposed at substantially the same level as the first surface of the first insulating layer; a second insulating layer disposed on a second surface of the first insulating layer and having a first surface in contact with the second surface of the first insulating layer; and a first wiring pattern embedded in the second insulating layer and exposed from the first surface of the second insulating layer to be in contact with a second externally exposed surface of the external connection pad opposing the first externally exposed surface.