Multilayer PCB Plane Conductor Formation via Selective Etching
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Solution Overview
Problem
Current methods for manufacturing multilayer printed wiring boards face challenges in forming fine-pitch circuit structures and achieving flat, level surfaces for plane conductors, leading to issues with insulation consistency and potential warping during heat cycles due to uneven copper volumes.
Innovation Solution
A method involving the formation of a first conductive circuit on a resin insulative material, followed by a second resin insulative material with specific concave portions and posts, allowing for even deposition of conductive material to create flat plane conductors, ensuring the surface is level with the resin insulative material and maintaining designed copper volumes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional semi-additive method is used to form circuits, then manufacturing process is simple, but fine-pitch circuit structure cannot be achieved with sufficient precision
Solution Approach 1:
The patent segments the circuit formation process into distinct steps: laser drilling of through-holes, electroless plating of conductor layers, and selective etching. This segmentation enables precise control over each step, achieving fine-pitch circuit structures while maintaining manufacturability through standardized process modules.
Solution Approach 2:
The patent applies preliminary action by pre-forming conductor layers through electroless plating before final circuit pattern definition. This preliminary conductor layer provides a foundation for subsequent selective removal and circuit formation, enabling higher precision in fine-pitch structures.
2Reliability
If copper volume is increased to ensure adequate conductivity, then electrical performance improves, but warping during heat cycles occurs due to uneven distribution
Solution Approach 1:
The patent applies local quality by varying copper distribution according to specific functional requirements. Through-holes and conductor paths receive copper where needed for electrical connectivity, while non-conductive areas remain free of copper. This localized copper placement ensures adequate conductivity in critical paths while preventing warping by eliminating unnecessary copper in non-conductive regions.
Solution Approach 2:
The patent changes the parameter of copper distribution from uniform to non-uniform based on functional requirements. By controlling copper deposition through electroless plating followed by selective etching, the patent achieves optimal copper volume in conductor paths while maintaining low copper content in non-conductive areas, thereby preventing warping during thermal cycling.
3Manufacturing precision
If plane conductor surface is made flat for better assembly, then insulation consistency improves, but manufacturing complexity increases due to additional processing steps
Solution Approach 1:
The patent applies preliminary action by forming conductor layers and defining circuit patterns before final planarization steps. The electroless plating and selective etching processes establish the copper geometry early, allowing subsequent steps to focus on surface flatness without compromising the already-defined circuit patterns.
Solution Approach 2:
The patent changes the surface topology parameter from potentially uneven to flat through controlled processing. By managing copper deposition and removal processes, the patent achieves flat plane conductor surfaces that improve insulation consistency and assembly quality, while the incremental nature of the process steps keeps manufacturing complexity manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of flat plane conductors, enhances insulation consistency between layers, and reduces warping risks during heat cycles by ensuring uniform copper deposition and controlled volumes, improving the overall performance and reliability of multilayer printed wiring boards.
Implementation Method 1
electroless plated film 352 and electrolytic plated film 356 are deposited in concave portion (353b) for forming a circuit, in opening 351 for forming a via conductor and in concave portion (353a) for forming a plane conductor
Implementation Method 2
electroless plated film 352 and electrolytic plated film 356 are deposited in concave portion (353b) for forming a circuit, in opening 351 for forming a via conductor and in concave portion (353a) for forming a plane conductor
Data Source
AI summary
A method for manufacturing a multilayer printed wiring board includes preparing a first resin insulative material having a first conductive circuit on or in the first resin insulative material, forming a second resin insulative material on the first resin insulative material and the first conductive circuit, forming on a surface of the second resin insulative material a first concave portion to be filled with a conductive material for formation of a second conductive circuit, forming on the surface of the second resin insulative material a pattern having a second concave portion and post portions to be filled with the conductive material for formation of a plane conductor, and filling the conductive material in the first concave portion and the second concave portion such that the second conductive circuit and the plane conductor are formed.