PCB Copper Plating Interface Control to Suppress Pattern Peeling
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Solution Overview
Problem
Existing printed circuit boards formed using the semi-additive method face issues with void density at the interface between the copper electroless plating layer and the copper electroplating layer, leading to side etching and peeling of the electrically conductive pattern from the base film, which is difficult to control due to contamination and resist pattern thickness.
Innovation Solution
The printed circuit board design includes a void density at the interface between the electrically conductive base layer and the copper electroplating layer ranging from more than 0.01 μm²/μm to 5.5 μm²/μm, with a product of the base layer thickness and void length ratio (T×VL/L) of 0.39 or less, to suppress peeling by managing side etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If void density at the interface between copper electroless plating layer and copper electroplating layer is increased, then manufacturing tolerance is relaxed, but side etching occurs causing peeling of electrically conductive pattern from base film
Solution Approach 1:
The patent changes the parameter of void density from the conventional requirement of 0.01 μm²/μm or less to a relaxed range of 0.03 μm²/μm to 5.5 μm²/μm, while simultaneously introducing a new parameter T×VL/L ≤ 0.39 to control the combined effect of base layer thickness and void characteristics. This parameter transformation allows higher void density without causing peeling.
Solution Approach 2:
The patent applies local quality by differentiating the requirements for different regions: the copper electroless plating layer thickness is controlled within 0.5 μm to 5 μm to provide adequate adhesion at the interface, while the copper electroplating layer thickness is controlled within 5 μm to 50 μm for electrical performance. This localized thickness control compensates for increased void density.
2Adaptability or versatility
If thick resist patterns are used or contamination is present, then pattern formation flexibility is improved, but void density increases leading to side etching and peeling
Solution Approach 1:
The patent introduces the parameter T×VL/L ≤ 0.39 as a pre-control measure to cushion against the harmful effects of increased void density. By controlling the product of base layer thickness and void length ratio before etching occurs, the patent prevents side etching and peeling that would otherwise result from high void density caused by thick resist patterns or contamination.
Solution Approach 2:
The patent converts the harmful effect of increased void density (which normally causes side etching) into a benefit by establishing that void density between 0.03 μm²/μm and 5.5 μm²/μm combined with T×VL/L ≤ 0.39 actually improves manufacturing flexibility. The controlled voids allow for thicker resist patterns and greater contamination tolerance while maintaining adhesion through the copper electroless plating layer thickness control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses the peeling of the electrically conductive pattern from the base film by controlling side etching, even with increased void density, ensuring the integrity of the circuit board.
Implementation Method 1
The copper electroless plating layer is disposed on the seed layer. The copper electroplating layer is disposed on the copper electroless plating layer. The copper electroless plating layer and the copper electroplating layer are formed of copper. That is, the electrically conductive pattern is formed by using a semi-additive method.
Implementation Method 2
The copper electroplating layer is disposed on the copper electroless plating layer. The copper electroless plating layer and the copper electroplating layer are formed of copper.
Data Source
AI summary
A printed circuit board includes a base film having a main surface, and an electrically conductive pattern disposed on the main surface. The electrically conductive pattern includes an electrically conductive base layer disposed on the main surface directly or indirectly, and a copper electroplating layer disposed on the electrically conductive base layer. The void density, being a value obtained by dividing a sum of areas of voids within a predetermined observation length at an interface between the electrically conductive base layer and the copper electroplating layer by the observation length, is more than 0.01 μm2/μm and 5.5 μm2/μm or less.